--- /dev/null
+From e1fbfa4a995d42e02e22b0dff2f8b4fdee1504b3 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 14 Nov 2023 15:08:42 +0100
+Subject: [PATCH 2/3] net: phy: aquantia: move MMD_VEND define to header
+
+Move MMD_VEND define to header to clean things up and in preparation for
+firmware loading support that require some define placed in
+aquantia_main.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/aquantia/aquantia.h | 69 +++++++++++++++++++++++
+ drivers/net/phy/aquantia/aquantia_hwmon.c | 14 -----
+ drivers/net/phy/aquantia/aquantia_main.c | 55 ------------------
+ 3 files changed, 69 insertions(+), 69 deletions(-)
+
+--- a/drivers/net/phy/aquantia/aquantia.h
++++ b/drivers/net/phy/aquantia/aquantia.h
+@@ -9,6 +9,75 @@
+ #include <linux/device.h>
+ #include <linux/phy.h>
+
++/* Vendor specific 1, MDIO_MMD_VEND1 */
++#define VEND1_GLOBAL_FW_ID 0x0020
++#define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8)
++#define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0)
++
++/* The following registers all have similar layouts; first the registers... */
++#define VEND1_GLOBAL_CFG_10M 0x0310
++#define VEND1_GLOBAL_CFG_100M 0x031b
++#define VEND1_GLOBAL_CFG_1G 0x031c
++#define VEND1_GLOBAL_CFG_2_5G 0x031d
++#define VEND1_GLOBAL_CFG_5G 0x031e
++#define VEND1_GLOBAL_CFG_10G 0x031f
++/* ...and now the fields */
++#define VEND1_GLOBAL_CFG_RATE_ADAPT GENMASK(8, 7)
++#define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE 0
++#define VEND1_GLOBAL_CFG_RATE_ADAPT_USX 1
++#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE 2
++
++/* Vendor specific 1, MDIO_MMD_VEND2 */
++#define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL 0xc421
++#define VEND1_THERMAL_PROV_LOW_TEMP_FAIL 0xc422
++#define VEND1_THERMAL_PROV_HIGH_TEMP_WARN 0xc423
++#define VEND1_THERMAL_PROV_LOW_TEMP_WARN 0xc424
++#define VEND1_THERMAL_STAT1 0xc820
++#define VEND1_THERMAL_STAT2 0xc821
++#define VEND1_THERMAL_STAT2_VALID BIT(0)
++#define VEND1_GENERAL_STAT1 0xc830
++#define VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL BIT(14)
++#define VEND1_GENERAL_STAT1_LOW_TEMP_FAIL BIT(13)
++#define VEND1_GENERAL_STAT1_HIGH_TEMP_WARN BIT(12)
++#define VEND1_GENERAL_STAT1_LOW_TEMP_WARN BIT(11)
++
++#define VEND1_GLOBAL_GEN_STAT2 0xc831
++#define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG BIT(15)
++
++#define VEND1_GLOBAL_RSVD_STAT1 0xc885
++#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4)
++#define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0)
++
++#define VEND1_GLOBAL_RSVD_STAT9 0xc88d
++#define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0)
++#define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23
++
++#define VEND1_GLOBAL_INT_STD_STATUS 0xfc00
++#define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01
++
++#define VEND1_GLOBAL_INT_STD_MASK 0xff00
++#define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15)
++#define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14)
++#define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13)
++#define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12)
++#define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11)
++#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10)
++#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9)
++#define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8)
++#define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7)
++#define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6)
++#define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0)
++
++#define VEND1_GLOBAL_INT_VEND_MASK 0xff01
++#define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15)
++#define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14)
++#define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13)
++#define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12)
++#define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11)
++#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2)
++#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1)
++#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0)
++
+ #if IS_REACHABLE(CONFIG_HWMON)
+ int aqr_hwmon_probe(struct phy_device *phydev);
+ #else
+--- a/drivers/net/phy/aquantia/aquantia_hwmon.c
++++ b/drivers/net/phy/aquantia/aquantia_hwmon.c
+@@ -13,20 +13,6 @@
+
+ #include "aquantia.h"
+
+-/* Vendor specific 1, MDIO_MMD_VEND2 */
+-#define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL 0xc421
+-#define VEND1_THERMAL_PROV_LOW_TEMP_FAIL 0xc422
+-#define VEND1_THERMAL_PROV_HIGH_TEMP_WARN 0xc423
+-#define VEND1_THERMAL_PROV_LOW_TEMP_WARN 0xc424
+-#define VEND1_THERMAL_STAT1 0xc820
+-#define VEND1_THERMAL_STAT2 0xc821
+-#define VEND1_THERMAL_STAT2_VALID BIT(0)
+-#define VEND1_GENERAL_STAT1 0xc830
+-#define VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL BIT(14)
+-#define VEND1_GENERAL_STAT1_LOW_TEMP_FAIL BIT(13)
+-#define VEND1_GENERAL_STAT1_HIGH_TEMP_WARN BIT(12)
+-#define VEND1_GENERAL_STAT1_LOW_TEMP_WARN BIT(11)
+-
+ #if IS_REACHABLE(CONFIG_HWMON)
+
+ static umode_t aqr_hwmon_is_visible(const void *data,
+--- a/drivers/net/phy/aquantia/aquantia_main.c
++++ b/drivers/net/phy/aquantia/aquantia_main.c
+@@ -89,61 +89,6 @@
+ #define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a
+ #define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b
+
+-/* Vendor specific 1, MDIO_MMD_VEND1 */
+-#define VEND1_GLOBAL_FW_ID 0x0020
+-#define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8)
+-#define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0)
+-
+-#define VEND1_GLOBAL_GEN_STAT2 0xc831
+-#define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG BIT(15)
+-
+-/* The following registers all have similar layouts; first the registers... */
+-#define VEND1_GLOBAL_CFG_10M 0x0310
+-#define VEND1_GLOBAL_CFG_100M 0x031b
+-#define VEND1_GLOBAL_CFG_1G 0x031c
+-#define VEND1_GLOBAL_CFG_2_5G 0x031d
+-#define VEND1_GLOBAL_CFG_5G 0x031e
+-#define VEND1_GLOBAL_CFG_10G 0x031f
+-/* ...and now the fields */
+-#define VEND1_GLOBAL_CFG_RATE_ADAPT GENMASK(8, 7)
+-#define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE 0
+-#define VEND1_GLOBAL_CFG_RATE_ADAPT_USX 1
+-#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE 2
+-
+-#define VEND1_GLOBAL_RSVD_STAT1 0xc885
+-#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4)
+-#define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0)
+-
+-#define VEND1_GLOBAL_RSVD_STAT9 0xc88d
+-#define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0)
+-#define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23
+-
+-#define VEND1_GLOBAL_INT_STD_STATUS 0xfc00
+-#define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01
+-
+-#define VEND1_GLOBAL_INT_STD_MASK 0xff00
+-#define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15)
+-#define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14)
+-#define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13)
+-#define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12)
+-#define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11)
+-#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10)
+-#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9)
+-#define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8)
+-#define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7)
+-#define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6)
+-#define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0)
+-
+-#define VEND1_GLOBAL_INT_VEND_MASK 0xff01
+-#define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15)
+-#define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14)
+-#define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13)
+-#define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12)
+-#define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11)
+-#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2)
+-#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1)
+-#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0)
+-
+ /* Sleep and timeout for checking if the Processor-Intensive
+ * MDIO operation is finished
+ */
projects / openwrt / openwrt.git / blobdiff