--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -537,7 +537,7 @@ static void mtk_set_queue_speed(struct m
+@@ -536,7 +536,7 @@ static void mtk_set_queue_speed(struct m
FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
if (IS_ENABLED(CONFIG_SOC_MT7621)) {
-@@ -912,7 +912,7 @@ static bool mtk_rx_get_desc(struct mtk_e
+@@ -911,7 +911,7 @@ static bool mtk_rx_get_desc(struct mtk_e
rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
rxd->rxd5 = READ_ONCE(dma_rxd->rxd5);
rxd->rxd6 = READ_ONCE(dma_rxd->rxd6);
}
-@@ -970,7 +970,7 @@ static int mtk_init_fq_dma(struct mtk_et
+@@ -969,7 +969,7 @@ static int mtk_init_fq_dma(struct mtk_et
txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
txd->txd4 = 0;
txd->txd5 = 0;
txd->txd6 = 0;
txd->txd7 = 0;
-@@ -1159,7 +1159,7 @@ static void mtk_tx_set_dma_desc(struct n
+@@ -1158,7 +1158,7 @@ static void mtk_tx_set_dma_desc(struct n
struct mtk_mac *mac = netdev_priv(dev);
struct mtk_eth *eth = mac->hw;
mtk_tx_set_dma_desc_v2(dev, txd, info);
else
mtk_tx_set_dma_desc_v1(dev, txd, info);
-@@ -1466,7 +1466,7 @@ static void mtk_update_rx_cpu_idx(struct
+@@ -1465,7 +1465,7 @@ static void mtk_update_rx_cpu_idx(struct
static bool mtk_page_pool_enabled(struct mtk_eth *eth)
{
}
static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth,
-@@ -1806,7 +1806,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1805,7 +1805,7 @@ static int mtk_poll_rx(struct napi_struc
break;
/* find out which mac the packet come from. values start at 1 */
mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1;
else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
!(trxd.rxd4 & RX_DMA_SPECIAL_TAG))
-@@ -1902,7 +1902,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1901,7 +1901,7 @@ static int mtk_poll_rx(struct napi_struc
skb->dev = netdev;
bytes += skb->len;
reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5);
hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY;
if (hash != MTK_RXD5_FOE_ENTRY)
-@@ -1927,8 +1927,8 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1926,8 +1926,8 @@ static int mtk_poll_rx(struct napi_struc
/* When using VLAN untagging in combination with DSA, the
* hardware treats the MTK special tag as a VLAN and untags it.
*/
unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0);
if (port < ARRAY_SIZE(eth->dsa_meta) &&
-@@ -2232,7 +2232,7 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2231,7 +2231,7 @@ static int mtk_tx_alloc(struct mtk_eth *
txd->txd2 = next_ptr;
txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
txd->txd4 = 0;
txd->txd5 = 0;
txd->txd6 = 0;
txd->txd7 = 0;
-@@ -2285,14 +2285,14 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2284,14 +2284,14 @@ static int mtk_tx_alloc(struct mtk_eth *
FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate + 4);
} else {
mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0);
-@@ -2419,7 +2419,7 @@ static int mtk_rx_alloc(struct mtk_eth *
+@@ -2418,7 +2418,7 @@ static int mtk_rx_alloc(struct mtk_eth *
rxd->rxd3 = 0;
rxd->rxd4 = 0;
rxd->rxd5 = 0;
rxd->rxd6 = 0;
rxd->rxd7 = 0;
-@@ -2970,7 +2970,7 @@ static int mtk_start_dma(struct mtk_eth
+@@ -2969,7 +2969,7 @@ static int mtk_start_dma(struct mtk_eth
MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO |
MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE;
val |= MTK_MUTLI_CNT | MTK_RESV_BUF |
MTK_WCOMP_EN | MTK_DMAD_WR_WDONE |
MTK_CHK_DDONE_EN | MTK_LEAKY_BUCKET_EN;
-@@ -3114,7 +3114,7 @@ static int mtk_open(struct net_device *d
+@@ -3113,7 +3113,7 @@ static int mtk_open(struct net_device *d
phylink_start(mac->phylink);
netif_tx_start_all_queues(dev);
return 0;
if (mtk_uses_dsa(dev) && !eth->prog) {
-@@ -3379,7 +3379,7 @@ static void mtk_hw_reset(struct mtk_eth
+@@ -3378,7 +3378,7 @@ static void mtk_hw_reset(struct mtk_eth
{
u32 val;
regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0);
val = RSTCTRL_PPE0_V2;
} else {
-@@ -3391,7 +3391,7 @@ static void mtk_hw_reset(struct mtk_eth
+@@ -3390,7 +3390,7 @@ static void mtk_hw_reset(struct mtk_eth
ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val);
regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
0x3ffffff);
}
-@@ -3417,7 +3417,7 @@ static void mtk_hw_warm_reset(struct mtk
+@@ -3416,7 +3416,7 @@ static void mtk_hw_warm_reset(struct mtk
return;
}
rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2;
else
rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0;
-@@ -3587,7 +3587,7 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3586,7 +3586,7 @@ static int mtk_hw_init(struct mtk_eth *e
else
mtk_hw_reset(eth);
/* Set FE to PDMAv2 if necessary */
val = mtk_r32(eth, MTK_FE_GLO_MISC);
mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC);
-@@ -3624,7 +3624,7 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3623,7 +3623,7 @@ static int mtk_hw_init(struct mtk_eth *e
*/
val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
val = mtk_r32(eth, MTK_CDMP_IG_CTRL);
mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL);
-@@ -3646,7 +3646,7 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3645,7 +3645,7 @@ static int mtk_hw_init(struct mtk_eth *e
mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4);
mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
/* PSE should not drop port8 and port9 packets from WDMA Tx */
mtk_w32(eth, 0x00000300, PSE_DROP_CFG);
-@@ -4435,7 +4435,7 @@ static int mtk_probe(struct platform_dev
+@@ -4434,7 +4434,7 @@ static int mtk_probe(struct platform_dev
}
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
err = -EINVAL;
-@@ -4543,9 +4543,8 @@ static int mtk_probe(struct platform_dev
+@@ -4542,9 +4542,8 @@ static int mtk_probe(struct platform_dev
}
if (eth->soc->offload_version) {
num_ppe = min_t(u32, ARRAY_SIZE(eth->ppe), num_ppe);
for (i = 0; i < num_ppe; i++) {
u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400;
-@@ -4639,6 +4638,7 @@ static const struct mtk_soc_data mt2701_
+@@ -4638,6 +4637,7 @@ static const struct mtk_soc_data mt2701_
.hw_features = MTK_HW_FEATURES,
.required_clks = MT7623_CLKS_BITMAP,
.required_pctl = true,
.txrx = {
.txd_size = sizeof(struct mtk_tx_dma),
.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -4655,6 +4655,7 @@ static const struct mtk_soc_data mt7621_
+@@ -4654,6 +4654,7 @@ static const struct mtk_soc_data mt7621_
.hw_features = MTK_HW_FEATURES,
.required_clks = MT7621_CLKS_BITMAP,
.required_pctl = false,
.offload_version = 1,
.hash_offset = 2,
.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
-@@ -4675,6 +4676,7 @@ static const struct mtk_soc_data mt7622_
+@@ -4674,6 +4675,7 @@ static const struct mtk_soc_data mt7622_
.hw_features = MTK_HW_FEATURES,
.required_clks = MT7622_CLKS_BITMAP,
.required_pctl = false,
.offload_version = 2,
.hash_offset = 2,
.has_accounting = true,
-@@ -4695,6 +4697,7 @@ static const struct mtk_soc_data mt7623_
+@@ -4694,6 +4696,7 @@ static const struct mtk_soc_data mt7623_
.hw_features = MTK_HW_FEATURES,
.required_clks = MT7623_CLKS_BITMAP,
.required_pctl = true,
.offload_version = 1,
.hash_offset = 2,
.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
-@@ -4717,6 +4720,7 @@ static const struct mtk_soc_data mt7629_
+@@ -4716,6 +4719,7 @@ static const struct mtk_soc_data mt7629_
.required_clks = MT7629_CLKS_BITMAP,
.required_pctl = false,
.has_accounting = true,
.txrx = {
.txd_size = sizeof(struct mtk_tx_dma),
.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -4734,6 +4738,7 @@ static const struct mtk_soc_data mt7981_
+@@ -4733,6 +4737,7 @@ static const struct mtk_soc_data mt7981_
.hw_features = MTK_HW_FEATURES,
.required_clks = MT7981_CLKS_BITMAP,
.required_pctl = false,
.offload_version = 2,
.hash_offset = 4,
.has_accounting = true,
-@@ -4755,6 +4760,7 @@ static const struct mtk_soc_data mt7986_
+@@ -4754,6 +4759,7 @@ static const struct mtk_soc_data mt7986_
.hw_features = MTK_HW_FEATURES,
.required_clks = MT7986_CLKS_BITMAP,
.required_pctl = false,
.offload_version = 2,
.hash_offset = 4,
.has_accounting = true,
-@@ -4775,6 +4781,7 @@ static const struct mtk_soc_data rt5350_
+@@ -4774,6 +4780,7 @@ static const struct mtk_soc_data rt5350_
.hw_features = MTK_HW_FEATURES_MT7628,
.required_clks = MT7628_CLKS_BITMAP,
.required_pctl = false,
else
val = MTK_FOE_IB2_MIB_CNT;
@@ -971,7 +971,7 @@ void mtk_ppe_start(struct mtk_ppe *ppe)
- MTK_PPE_SCAN_MODE_KEEPALIVE_AGE) |
+ MTK_PPE_SCAN_MODE_CHECK_AGE) |
FIELD_PREP(MTK_PPE_TB_CFG_ENTRY_NUM,
MTK_PPE_ENTRIES_SHIFT);
- if (MTK_HAS_CAPS(ppe->eth->soc->caps, MTK_NETSYS_V2))