generic: 5.15: qca8k: add kernel version tag on backport patch

[openwrt/staging/svanheule.git] / target / linux / generic / backport-5.15 / 766-v5.18-14-net-dsa-qca8k-cache-lo-and-hi-for-mdio-write.patch

diff --git a/target/linux/generic/backport-5.15/766-v5.18-14-net-dsa-qca8k-cache-lo-and-hi-for-mdio-write.patch b/target/linux/generic/backport-5.15/766-v5.18-14-net-dsa-qca8k-cache-lo-and-hi-for-mdio-write.patch
new file mode 100644 (file)
index 0000000..e2cb272
--- /dev/null
+++ b/target/linux/generic/backport-5.15/766-v5.18-14-net-dsa-qca8k-cache-lo-and-hi-for-mdio-write.patch
@@ -0,0 +1,164 @@
+From 2481d206fae7884cd07014fd1318e63af35e99eb Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Wed, 2 Feb 2022 01:03:33 +0100
+Subject: [PATCH 14/16] net: dsa: qca8k: cache lo and hi for mdio write
+
+From Documentation, we can cache lo and hi the same way we do with the
+page. This massively reduce the mdio write as 3/4 of the time as we only
+require to write the lo or hi part for a mdio write.
+
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/qca8k.c | 61 +++++++++++++++++++++++++++++++++--------
+ drivers/net/dsa/qca8k.h |  5 ++++
+ 2 files changed, 54 insertions(+), 12 deletions(-)
+
+--- a/drivers/net/dsa/qca8k.c
++++ b/drivers/net/dsa/qca8k.c
+@@ -89,6 +89,44 @@ qca8k_split_addr(u32 regaddr, u16 *r1, u
+ }
+ 
+ static int
++qca8k_set_lo(struct qca8k_priv *priv, int phy_id, u32 regnum, u16 lo)
++{
++      u16 *cached_lo = &priv->mdio_cache.lo;
++      struct mii_bus *bus = priv->bus;
++      int ret;
++
++      if (lo == *cached_lo)
++              return 0;
++
++      ret = bus->write(bus, phy_id, regnum, lo);
++      if (ret < 0)
++              dev_err_ratelimited(&bus->dev,
++                                  "failed to write qca8k 32bit lo register\n");
++
++      *cached_lo = lo;
++      return 0;
++}
++
++static int
++qca8k_set_hi(struct qca8k_priv *priv, int phy_id, u32 regnum, u16 hi)
++{
++      u16 *cached_hi = &priv->mdio_cache.hi;
++      struct mii_bus *bus = priv->bus;
++      int ret;
++
++      if (hi == *cached_hi)
++              return 0;
++
++      ret = bus->write(bus, phy_id, regnum, hi);
++      if (ret < 0)
++              dev_err_ratelimited(&bus->dev,
++                                  "failed to write qca8k 32bit hi register\n");
++
++      *cached_hi = hi;
++      return 0;
++}
++
++static int
+ qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
+ {
+       int ret;
+@@ -111,7 +149,7 @@ qca8k_mii_read32(struct mii_bus *bus, in
+ }
+ 
+ static void
+-qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
++qca8k_mii_write32(struct qca8k_priv *priv, int phy_id, u32 regnum, u32 val)
+ {
+       u16 lo, hi;
+       int ret;
+@@ -119,12 +157,9 @@ qca8k_mii_write32(struct mii_bus *bus, i
+       lo = val & 0xffff;
+       hi = (u16)(val >> 16);
+ 
+-      ret = bus->write(bus, phy_id, regnum, lo);
++      ret = qca8k_set_lo(priv, phy_id, regnum, lo);
+       if (ret >= 0)
+-              ret = bus->write(bus, phy_id, regnum + 1, hi);
+-      if (ret < 0)
+-              dev_err_ratelimited(&bus->dev,
+-                                  "failed to write qca8k 32bit register\n");
++              ret = qca8k_set_hi(priv, phy_id, regnum + 1, hi);
+ }
+ 
+ static int
+@@ -400,7 +435,7 @@ qca8k_regmap_write(void *ctx, uint32_t r
+       if (ret < 0)
+               goto exit;
+ 
+-      qca8k_mii_write32(bus, 0x10 | r2, r1, val);
++      qca8k_mii_write32(priv, 0x10 | r2, r1, val);
+ 
+ exit:
+       mutex_unlock(&bus->mdio_lock);
+@@ -433,7 +468,7 @@ qca8k_regmap_update_bits(void *ctx, uint
+ 
+       val &= ~mask;
+       val |= write_val;
+-      qca8k_mii_write32(bus, 0x10 | r2, r1, val);
++      qca8k_mii_write32(priv, 0x10 | r2, r1, val);
+ 
+ exit:
+       mutex_unlock(&bus->mdio_lock);
+@@ -1117,14 +1152,14 @@ qca8k_mdio_write(struct qca8k_priv *priv
+       if (ret)
+               goto exit;
+ 
+-      qca8k_mii_write32(bus, 0x10 | r2, r1, val);
++      qca8k_mii_write32(priv, 0x10 | r2, r1, val);
+ 
+       ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
+                                  QCA8K_MDIO_MASTER_BUSY);
+ 
+ exit:
+       /* even if the busy_wait timeouts try to clear the MASTER_EN */
+-      qca8k_mii_write32(bus, 0x10 | r2, r1, 0);
++      qca8k_mii_write32(priv, 0x10 | r2, r1, 0);
+ 
+       mutex_unlock(&bus->mdio_lock);
+ 
+@@ -1154,7 +1189,7 @@ qca8k_mdio_read(struct qca8k_priv *priv,
+       if (ret)
+               goto exit;
+ 
+-      qca8k_mii_write32(bus, 0x10 | r2, r1, val);
++      qca8k_mii_write32(priv, 0x10 | r2, r1, val);
+ 
+       ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
+                                  QCA8K_MDIO_MASTER_BUSY);
+@@ -1165,7 +1200,7 @@ qca8k_mdio_read(struct qca8k_priv *priv,
+ 
+ exit:
+       /* even if the busy_wait timeouts try to clear the MASTER_EN */
+-      qca8k_mii_write32(bus, 0x10 | r2, r1, 0);
++      qca8k_mii_write32(priv, 0x10 | r2, r1, 0);
+ 
+       mutex_unlock(&bus->mdio_lock);
+ 
+@@ -3057,6 +3092,8 @@ qca8k_sw_probe(struct mdio_device *mdiod
+       }
+ 
+       priv->mdio_cache.page = 0xffff;
++      priv->mdio_cache.lo = 0xffff;
++      priv->mdio_cache.hi = 0xffff;
+ 
+       /* Check the detected switch id */
+       ret = qca8k_read_switch_id(priv);
+--- a/drivers/net/dsa/qca8k.h
++++ b/drivers/net/dsa/qca8k.h
+@@ -369,6 +369,11 @@ struct qca8k_mdio_cache {
+  * mdio writes
+  */
+       u16 page;
++/* lo and hi can also be cached and from Documentation we can skip one
++ * extra mdio write if lo or hi is didn't change.
++ */
++      u16 lo;
++      u16 hi;
+ };
+ 
+ struct qca8k_priv {