--- /dev/null
+From 0dcde4c1e7c47822a6b00d6f96b7f19e51536026 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Jan 2024 08:35:55 +0300
+Subject: [PATCH 26/48] net: dsa: mt7530: improve comments regarding switch
+ ports
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+There's no logic to numerically order the CPU ports. Just state the port
+number instead.
+
+Remove the irrelevant PHY muxing information from
+mt7530_mac_port_get_caps(). Explain the supported MII modes instead.
+
+Remove the out of place PHY muxing information from
+mt753x_phylink_mac_config(). The function is for MT7530, MT7531, and the
+switch on the MT7988 SoC but there's no PHY muxing on MT7531 or the switch
+on the MT7988 SoC.
+
+These comments were gradually introduced with the commits below.
+commit ca366d6c889b ("net: dsa: mt7530: Convert to PHYLINK API")
+commit 38f790a80560 ("net: dsa: mt7530: Add support for port 5")
+commit 88bdef8be9f6 ("net: dsa: mt7530: Extend device data ready for adding
+a new hardware")
+commit c288575f7810 ("net: dsa: mt7530: Add the support of MT7531 switch")
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Acked-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Link: https://lore.kernel.org/r/20240122-for-netnext-mt7530-improvements-1-v3-4-042401f2b279@arinc9.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 30 ++++++++++++++++++++----------
+ 1 file changed, 20 insertions(+), 10 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2565,12 +2565,14 @@ static void mt7530_mac_port_get_caps(str
+ struct phylink_config *config)
+ {
+ switch (port) {
+- case 0 ... 4: /* Internal phy */
++ /* Ports which are connected to switch PHYs. There is no MII pinout. */
++ case 0 ... 4:
+ __set_bit(PHY_INTERFACE_MODE_GMII,
+ config->supported_interfaces);
+ break;
+
+- case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
++ /* Port 5 supports rgmii with delays, mii, and gmii. */
++ case 5:
+ phy_interface_set_rgmii(config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_MII,
+ config->supported_interfaces);
+@@ -2578,7 +2580,8 @@ static void mt7530_mac_port_get_caps(str
+ config->supported_interfaces);
+ break;
+
+- case 6: /* 1st cpu port */
++ /* Port 6 supports rgmii and trgmii. */
++ case 6:
+ __set_bit(PHY_INTERFACE_MODE_RGMII,
+ config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_TRGMII,
+@@ -2593,19 +2596,24 @@ static void mt7531_mac_port_get_caps(str
+ struct mt7530_priv *priv = ds->priv;
+
+ switch (port) {
+- case 0 ... 4: /* Internal phy */
++ /* Ports which are connected to switch PHYs. There is no MII pinout. */
++ case 0 ... 4:
+ __set_bit(PHY_INTERFACE_MODE_GMII,
+ config->supported_interfaces);
+ break;
+
+- case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */
++ /* Port 5 supports rgmii with delays on MT7531BE, sgmii/802.3z on
++ * MT7531AE.
++ */
++ case 5:
+ if (!priv->p5_sgmii) {
+ phy_interface_set_rgmii(config->supported_interfaces);
+ break;
+ }
+ fallthrough;
+
+- case 6: /* 1st cpu port supports sgmii/8023z only */
++ /* Port 6 supports sgmii/802.3z. */
++ case 6:
+ __set_bit(PHY_INTERFACE_MODE_SGMII,
+ config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_1000BASEX,
+@@ -2624,11 +2632,13 @@ static void mt7988_mac_port_get_caps(str
+ phy_interface_zero(config->supported_interfaces);
+
+ switch (port) {
+- case 0 ... 4: /* Internal phy */
++ /* Ports which are connected to switch PHYs. There is no MII pinout. */
++ case 0 ... 4:
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ config->supported_interfaces);
+ break;
+
++ /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */
+ case 6:
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ config->supported_interfaces);
+@@ -2792,12 +2802,12 @@ mt753x_phylink_mac_config(struct dsa_swi
+ u32 mcr_cur, mcr_new;
+
+ switch (port) {
+- case 0 ... 4: /* Internal phy */
++ case 0 ... 4:
+ if (state->interface != PHY_INTERFACE_MODE_GMII &&
+ state->interface != PHY_INTERFACE_MODE_INTERNAL)
+ goto unsupported;
+ break;
+- case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
++ case 5:
+ if (priv->p5_interface == state->interface)
+ break;
+
+@@ -2807,7 +2817,7 @@ mt753x_phylink_mac_config(struct dsa_swi
+ if (priv->p5_intf_sel != P5_DISABLED)
+ priv->p5_interface = state->interface;
+ break;
+- case 6: /* 1st cpu port */
++ case 6:
+ if (priv->p6_interface == state->interface)
+ break;
+
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