+++ /dev/null
-From 663fa1b7e0cb2c929008482014a70c6625caad75 Mon Sep 17 00:00:00 2001
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Tue, 7 Mar 2023 15:55:13 +0000
-Subject: [PATCH 1/7] net: ethernet: mtk_eth_soc: add MTK_NETSYS_V1 capability
- bit
-
-Introduce MTK_NETSYS_V1 bit in the device capabilities for
-MT7621/MT7622/MT7623/MT7628/MT7629 SoCs.
-Use !MTK_NETSYS_V1 instead of MTK_NETSYS_V2 in the driver codebase.
-This is a preliminary patch to introduce support for MT7988 SoC.
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 30 +++++++-------
- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 45 ++++++++++++---------
- 2 files changed, 41 insertions(+), 34 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -597,7 +597,7 @@ static void mtk_set_queue_speed(struct m
- FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
- FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
- MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
-- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
-+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1))
- val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
-
- if (IS_ENABLED(CONFIG_SOC_MT7621)) {
-@@ -974,7 +974,7 @@ static bool mtk_rx_get_desc(struct mtk_e
- rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
- rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
- rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
-- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
-+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) {
- rxd->rxd5 = READ_ONCE(dma_rxd->rxd5);
- rxd->rxd6 = READ_ONCE(dma_rxd->rxd6);
- }
-@@ -1032,7 +1032,7 @@ static int mtk_init_fq_dma(struct mtk_et
-
- txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
- txd->txd4 = 0;
-- if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) {
-+ if (!MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V1)) {
- txd->txd5 = 0;
- txd->txd6 = 0;
- txd->txd7 = 0;
-@@ -1221,7 +1221,7 @@ static void mtk_tx_set_dma_desc(struct n
- struct mtk_mac *mac = netdev_priv(dev);
- struct mtk_eth *eth = mac->hw;
-
-- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
-+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1))
- mtk_tx_set_dma_desc_v2(dev, txd, info);
- else
- mtk_tx_set_dma_desc_v1(dev, txd, info);
-@@ -1902,7 +1902,7 @@ static int mtk_poll_rx(struct napi_struc
- break;
-
- /* find out which mac the packet come from. values start at 1 */
-- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
-+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1))
- mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1;
- else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
- !(trxd.rxd4 & RX_DMA_SPECIAL_TAG))
-@@ -1998,7 +1998,7 @@ static int mtk_poll_rx(struct napi_struc
- skb->dev = netdev;
- bytes += skb->len;
-
-- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
-+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) {
- reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5);
- hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY;
- if (hash != MTK_RXD5_FOE_ENTRY)
-@@ -2023,7 +2023,7 @@ static int mtk_poll_rx(struct napi_struc
- /* When using VLAN untagging in combination with DSA, the
- * hardware treats the MTK special tag as a VLAN and untags it.
- */
-- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) &&
-+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1) &&
- (trxd.rxd2 & RX_DMA_VTAG) && netdev_uses_dsa(netdev)) {
- unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0);
-
-@@ -2328,7 +2328,7 @@ static int mtk_tx_alloc(struct mtk_eth *
- txd->txd2 = next_ptr;
- txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
- txd->txd4 = 0;
-- if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) {
-+ if (!MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V1)) {
- txd->txd5 = 0;
- txd->txd6 = 0;
- txd->txd7 = 0;
-@@ -2381,7 +2381,7 @@ static int mtk_tx_alloc(struct mtk_eth *
- FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
- FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
- MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
-- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
-+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1))
- val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
- mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
- ofs += MTK_QTX_OFFSET;
-@@ -2515,7 +2515,7 @@ static int mtk_rx_alloc(struct mtk_eth *
-
- rxd->rxd3 = 0;
- rxd->rxd4 = 0;
-- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
-+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) {
- rxd->rxd5 = 0;
- rxd->rxd6 = 0;
- rxd->rxd7 = 0;
-@@ -3063,7 +3063,7 @@ static int mtk_start_dma(struct mtk_eth
- MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO |
- MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE;
-
-- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
-+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1))
- val |= MTK_MUTLI_CNT | MTK_RESV_BUF |
- MTK_WCOMP_EN | MTK_DMAD_WR_WDONE |
- MTK_CHK_DDONE_EN | MTK_LEAKY_BUCKET_EN;
-@@ -3475,7 +3475,7 @@ static void mtk_hw_reset(struct mtk_eth
- {
- u32 val;
-
-- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
-+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) {
- regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0);
- val = RSTCTRL_PPE0_V2;
- } else {
-@@ -3487,7 +3487,7 @@ static void mtk_hw_reset(struct mtk_eth
-
- ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val);
-
-- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
-+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1))
- regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
- 0x3ffffff);
- }
-@@ -3683,7 +3683,7 @@ static int mtk_hw_init(struct mtk_eth *e
- else
- mtk_hw_reset(eth);
-
-- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
-+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) {
- /* Set FE to PDMAv2 if necessary */
- val = mtk_r32(eth, MTK_FE_GLO_MISC);
- mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC);
-@@ -3720,7 +3720,7 @@ static int mtk_hw_init(struct mtk_eth *e
- */
- val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
- mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
-- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
-+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) {
- val = mtk_r32(eth, MTK_CDMP_IG_CTRL);
- mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL);
-
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -816,6 +816,7 @@ enum mkt_eth_capabilities {
- MTK_SHARED_INT_BIT,
- MTK_TRGMII_MT7621_CLK_BIT,
- MTK_QDMA_BIT,
-+ MTK_NETSYS_V1_BIT,
- MTK_NETSYS_V2_BIT,
- MTK_SOC_MT7628_BIT,
- MTK_RSTCTRL_PPE1_BIT,
-@@ -851,6 +852,7 @@ enum mkt_eth_capabilities {
- #define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT)
- #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT)
- #define MTK_QDMA BIT(MTK_QDMA_BIT)
-+#define MTK_NETSYS_V1 BIT(MTK_NETSYS_V1_BIT)
- #define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT)
- #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT)
- #define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT)
-@@ -913,25 +915,30 @@ enum mkt_eth_capabilities {
-
- #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x) & ~(MTK_CAP_MASK)) == (_x))
-
--#define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
-- MTK_GMAC2_RGMII | MTK_SHARED_INT | \
-- MTK_TRGMII_MT7621_CLK | MTK_QDMA)
--
--#define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \
-- MTK_GMAC2_SGMII | MTK_GDM1_ESW | \
-- MTK_MUX_GDM1_TO_GMAC1_ESW | \
-- MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA)
--
--#define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \
-- MTK_QDMA)
--
--#define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628)
--
--#define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
-- MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \
-- MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \
-- MTK_MUX_U3_GMAC2_TO_QPHY | \
-- MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA)
-+#define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
-+ MTK_GMAC2_RGMII | MTK_SHARED_INT | \
-+ MTK_TRGMII_MT7621_CLK | MTK_QDMA | \
-+ MTK_NETSYS_V1)
-+
-+#define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | \
-+ MTK_GMAC2_RGMII | MTK_GMAC2_SGMII | \
-+ MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW |\
-+ MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | \
-+ MTK_QDMA | MTK_NETSYS_V1)
-+
-+#define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
-+ MTK_GMAC2_RGMII | MTK_QDMA | \
-+ MTK_NETSYS_V1)
-+
-+#define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628 | \
-+ MTK_NETSYS_V1)
-+
-+#define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
-+ MTK_GMAC2_GEPHY | MTK_GDM1_ESW | \
-+ MTK_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_QDMA | \
-+ MTK_MUX_U3_GMAC2_TO_QPHY | MTK_NETSYS_V1 |\
-+ MTK_MUX_GDM1_TO_GMAC1_ESW | \
-+ MTK_MUX_GMAC12_TO_GEPHY_SGMII)
-
- #define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
- MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
projects / openwrt / staging / dangole.git / blobdiff