--- /dev/null
+From 712ad00d2f43814c81a7abfcbc339690a05fb6a0 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:09 +0300
+Subject: [PATCH 02/15] net: dsa: mt7530: refactor MT7530_PMCR_P()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The MT7530_PMCR_P() registers are on MT7530, MT7531, and the switch on the
+MT7988 SoC. Rename the definition for them to MT753X_PMCR_P(). Bit 15 is
+for MT7530 only. Add MT7530 prefix to the definition for bit 15.
+
+Use GENMASK and FIELD_PREP for PMCR_IFG_XMIT().
+
+Rename PMCR_TX_EN and PMCR_RX_EN to PMCR_MAC_TX_EN and PMCR_MAC_TX_EN to
+follow the naming on the "MT7621 Giga Switch Programming Guide v0.3",
+"MT7531 Reference Manual for Development Board v1.0", and "MT7988A Wi-Fi 7
+Generation Router Platform: Datasheet (Open Version) v0.1" documents.
+
+These documents show that PMCR_RX_FC_EN is at bit 5. Correct this along
+with renaming it to PMCR_FORCE_RX_FC_EN, and the same for PMCR_TX_FC_EN.
+
+Remove PMCR_SPEED_MASK which doesn't have a use.
+
+Rename the force mode definitions for MT7531 to FORCE_MODE. Add MASK at the
+end for the mask that includes all force mode definitions.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 24 ++++++++---------
+ drivers/net/dsa/mt7530.h | 58 +++++++++++++++++++++-------------------
+ 2 files changed, 42 insertions(+), 40 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -889,7 +889,7 @@ static void mt7530_setup_port5(struct ds
+ val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
+
+ /* Setup the MAC by default for the cpu port */
+- mt7530_write(priv, MT7530_PMCR_P(5), 0x56300);
++ mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
+ break;
+ case P5_INTF_SEL_GMAC5:
+ /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
+@@ -2435,8 +2435,8 @@ mt7530_setup(struct dsa_switch *ds)
+ /* Clear link settings and enable force mode to force link down
+ * on all ports until they're enabled later.
+ */
+- mt7530_rmw(priv, MT7530_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
+- PMCR_FORCE_MODE, PMCR_FORCE_MODE);
++ mt7530_rmw(priv, MT753X_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
++ MT7530_FORCE_MODE, MT7530_FORCE_MODE);
+
+ /* Disable forwarding by default on all ports */
+ mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
+@@ -2546,8 +2546,8 @@ mt7531_setup_common(struct dsa_switch *d
+ /* Clear link settings and enable force mode to force link down
+ * on all ports until they're enabled later.
+ */
+- mt7530_rmw(priv, MT7530_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
+- MT7531_FORCE_MODE, MT7531_FORCE_MODE);
++ mt7530_rmw(priv, MT753X_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
++ MT7531_FORCE_MODE_MASK, MT7531_FORCE_MODE_MASK);
+
+ /* Disable forwarding by default on all ports */
+ mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
+@@ -2630,7 +2630,7 @@ mt7531_setup(struct dsa_switch *ds)
+
+ /* Force link down on all ports before internal reset */
+ for (i = 0; i < MT7530_NUM_PORTS; i++)
+- mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK);
++ mt7530_write(priv, MT753X_PMCR_P(i), MT7531_FORCE_MODE_LNK);
+
+ /* Reset the switch through internal reset */
+ mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_SW_RST | SYS_CTRL_REG_RST);
+@@ -2872,7 +2872,7 @@ mt753x_phylink_mac_config(struct phylink
+
+ /* Are we connected to external phy */
+ if (port == 5 && dsa_is_user_port(ds, 5))
+- mt7530_set(priv, MT7530_PMCR_P(port), PMCR_EXT_PHY);
++ mt7530_set(priv, MT753X_PMCR_P(port), PMCR_EXT_PHY);
+ }
+
+ static void mt753x_phylink_mac_link_down(struct phylink_config *config,
+@@ -2882,7 +2882,7 @@ static void mt753x_phylink_mac_link_down
+ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct mt7530_priv *priv = dp->ds->priv;
+
+- mt7530_clear(priv, MT7530_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK);
++ mt7530_clear(priv, MT753X_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK);
+ }
+
+ static void mt753x_phylink_mac_link_up(struct phylink_config *config,
+@@ -2896,7 +2896,7 @@ static void mt753x_phylink_mac_link_up(s
+ struct mt7530_priv *priv = dp->ds->priv;
+ u32 mcr;
+
+- mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
++ mcr = PMCR_MAC_RX_EN | PMCR_MAC_TX_EN | PMCR_FORCE_LNK;
+
+ switch (speed) {
+ case SPEED_1000:
+@@ -2911,9 +2911,9 @@ static void mt753x_phylink_mac_link_up(s
+ if (duplex == DUPLEX_FULL) {
+ mcr |= PMCR_FORCE_FDX;
+ if (tx_pause)
+- mcr |= PMCR_TX_FC_EN;
++ mcr |= PMCR_FORCE_TX_FC_EN;
+ if (rx_pause)
+- mcr |= PMCR_RX_FC_EN;
++ mcr |= PMCR_FORCE_RX_FC_EN;
+ }
+
+ if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) {
+@@ -2928,7 +2928,7 @@ static void mt753x_phylink_mac_link_up(s
+ }
+ }
+
+- mt7530_set(priv, MT7530_PMCR_P(dp->index), mcr);
++ mt7530_set(priv, MT753X_PMCR_P(dp->index), mcr);
+ }
+
+ static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -304,44 +304,46 @@ enum mt7530_vlan_port_acc_frm {
+ #define G0_PORT_VID_DEF G0_PORT_VID(0)
+
+ /* Register for port MAC control register */
+-#define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100))
+-#define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18)
++#define MT753X_PMCR_P(x) (0x3000 + ((x) * 0x100))
++#define PMCR_IFG_XMIT_MASK GENMASK(19, 18)
++#define PMCR_IFG_XMIT(x) FIELD_PREP(PMCR_IFG_XMIT_MASK, x)
+ #define PMCR_EXT_PHY BIT(17)
+ #define PMCR_MAC_MODE BIT(16)
+-#define PMCR_FORCE_MODE BIT(15)
+-#define PMCR_TX_EN BIT(14)
+-#define PMCR_RX_EN BIT(13)
++#define MT7530_FORCE_MODE BIT(15)
++#define PMCR_MAC_TX_EN BIT(14)
++#define PMCR_MAC_RX_EN BIT(13)
+ #define PMCR_BACKOFF_EN BIT(9)
+ #define PMCR_BACKPR_EN BIT(8)
+ #define PMCR_FORCE_EEE1G BIT(7)
+ #define PMCR_FORCE_EEE100 BIT(6)
+-#define PMCR_TX_FC_EN BIT(5)
+-#define PMCR_RX_FC_EN BIT(4)
++#define PMCR_FORCE_RX_FC_EN BIT(5)
++#define PMCR_FORCE_TX_FC_EN BIT(4)
+ #define PMCR_FORCE_SPEED_1000 BIT(3)
+ #define PMCR_FORCE_SPEED_100 BIT(2)
+ #define PMCR_FORCE_FDX BIT(1)
+ #define PMCR_FORCE_LNK BIT(0)
+-#define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 | \
+- PMCR_FORCE_SPEED_1000)
+-#define MT7531_FORCE_LNK BIT(31)
+-#define MT7531_FORCE_SPD BIT(30)
+-#define MT7531_FORCE_DPX BIT(29)
+-#define MT7531_FORCE_RX_FC BIT(28)
+-#define MT7531_FORCE_TX_FC BIT(27)
+-#define MT7531_FORCE_EEE100 BIT(26)
+-#define MT7531_FORCE_EEE1G BIT(25)
+-#define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \
+- MT7531_FORCE_SPD | \
+- MT7531_FORCE_DPX | \
+- MT7531_FORCE_RX_FC | \
+- MT7531_FORCE_TX_FC | \
+- MT7531_FORCE_EEE100 | \
+- MT7531_FORCE_EEE1G)
+-#define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \
+- PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \
+- PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
+- PMCR_FORCE_FDX | PMCR_FORCE_LNK | \
+- PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100)
++#define MT7531_FORCE_MODE_LNK BIT(31)
++#define MT7531_FORCE_MODE_SPD BIT(30)
++#define MT7531_FORCE_MODE_DPX BIT(29)
++#define MT7531_FORCE_MODE_RX_FC BIT(28)
++#define MT7531_FORCE_MODE_TX_FC BIT(27)
++#define MT7531_FORCE_MODE_EEE100 BIT(26)
++#define MT7531_FORCE_MODE_EEE1G BIT(25)
++#define MT7531_FORCE_MODE_MASK (MT7531_FORCE_MODE_LNK | \
++ MT7531_FORCE_MODE_SPD | \
++ MT7531_FORCE_MODE_DPX | \
++ MT7531_FORCE_MODE_RX_FC | \
++ MT7531_FORCE_MODE_TX_FC | \
++ MT7531_FORCE_MODE_EEE100 | \
++ MT7531_FORCE_MODE_EEE1G)
++#define PMCR_LINK_SETTINGS_MASK (PMCR_MAC_TX_EN | PMCR_MAC_RX_EN | \
++ PMCR_FORCE_EEE1G | \
++ PMCR_FORCE_EEE100 | \
++ PMCR_FORCE_RX_FC_EN | \
++ PMCR_FORCE_TX_FC_EN | \
++ PMCR_FORCE_SPEED_1000 | \
++ PMCR_FORCE_SPEED_100 | \
++ PMCR_FORCE_FDX | PMCR_FORCE_LNK)
+
+ #define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100)
+ #define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24)
projects / openwrt / openwrt.git / blobdiff