generic: 6.1, 6.6: mt7530: import pending patches

[openwrt/openwrt.git] / target / linux / generic / pending-6.6 / 745-07-net-dsa-mt7530-move-MT753X_MTRAP-operations-for-MT75.patch

diff --git a/target/linux/generic/pending-6.6/745-07-net-dsa-mt7530-move-MT753X_MTRAP-operations-for-MT75.patch b/target/linux/generic/pending-6.6/745-07-net-dsa-mt7530-move-MT753X_MTRAP-operations-for-MT75.patch
new file mode 100644 (file)
index 0000000..f7802c0
--- /dev/null
+++ b/target/linux/generic/pending-6.6/745-07-net-dsa-mt7530-move-MT753X_MTRAP-operations-for-MT75.patch
@@ -0,0 +1,117 @@
+From 2982f395c9a513b168f1e685588f70013cba2f5f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:14 +0300
+Subject: [PATCH 07/15] net: dsa: mt7530: move MT753X_MTRAP operations for
+ MT7530
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+On MT7530, the media-independent interfaces of port 5 and 6 are controlled
+by the MT7530_P5_DIS and MT7530_P6_DIS bits of the hardware trap. Deal with
+these bits only when the relevant port is being enabled or disabled. This
+ensures that these ports will be disabled when they are not in use.
+
+Do not set MT7530_CHG_TRAP on mt7530_setup_port5() as that's already being
+done on mt7530_setup().
+
+Instead of globally setting MT7530_P5_MAC_SEL, clear it, then set it only
+on the appropriate case.
+
+If PHY muxing is detected, clear MT7530_P5_DIS before calling
+mt7530_setup_port5().
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 38 +++++++++++++++++++++++++++-----------
+ 1 file changed, 27 insertions(+), 11 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -880,8 +880,7 @@ static void mt7530_setup_port5(struct ds
+ 
+       val = mt7530_read(priv, MT753X_MTRAP);
+ 
+-      val |= MT7530_CHG_TRAP | MT7530_P5_MAC_SEL | MT7530_P5_DIS;
+-      val &= ~MT7530_P5_RGMII_MODE & ~MT7530_P5_PHY0_SEL;
++      val &= ~MT7530_P5_PHY0_SEL & ~MT7530_P5_MAC_SEL & ~MT7530_P5_RGMII_MODE;
+ 
+       switch (priv->p5_mode) {
+       /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */
+@@ -891,15 +890,13 @@ static void mt7530_setup_port5(struct ds
+ 
+       /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */
+       case MUX_PHY_P4:
+-              val &= ~MT7530_P5_MAC_SEL & ~MT7530_P5_DIS;
+-
+               /* Setup the MAC by default for the cpu port */
+               mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
+               break;
+ 
+       /* GMAC5: P5 -> SoC MAC or external PHY */
+       default:
+-              val &= ~MT7530_P5_DIS;
++              val |= MT7530_P5_MAC_SEL;
+               break;
+       }
+ 
+@@ -1193,6 +1190,14 @@ mt7530_port_enable(struct dsa_switch *ds
+ 
+       mutex_unlock(&priv->reg_mutex);
+ 
++      if (priv->id != ID_MT7530 && priv->id != ID_MT7621)
++              return 0;
++
++      if (port == 5)
++              mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS);
++      else if (port == 6)
++              mt7530_clear(priv, MT753X_MTRAP, MT7530_P6_DIS);
++
+       return 0;
+ }
+ 
+@@ -1211,6 +1216,14 @@ mt7530_port_disable(struct dsa_switch *d
+                  PCR_MATRIX_CLR);
+ 
+       mutex_unlock(&priv->reg_mutex);
++
++      if (priv->id != ID_MT7530 && priv->id != ID_MT7621)
++              return;
++
++      if (port == 5)
++              mt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS);
++      else if (port == 6)
++              mt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS);
+ }
+ 
+ static int
+@@ -2401,11 +2414,11 @@ mt7530_setup(struct dsa_switch *ds)
+               mt7530_rmw(priv, MT7530_TRGMII_RD(i),
+                          RD_TAP_MASK, RD_TAP(16));
+ 
+-      /* Enable port 6 */
+-      val = mt7530_read(priv, MT753X_MTRAP);
+-      val &= ~MT7530_P6_DIS & ~MT7530_PHY_INDIRECT_ACCESS;
+-      val |= MT7530_CHG_TRAP;
+-      mt7530_write(priv, MT753X_MTRAP, val);
++      /* Allow modifying the trap and directly access PHY registers via the
++       * MDIO bus the switch is on.
++       */
++      mt7530_rmw(priv, MT753X_MTRAP, MT7530_CHG_TRAP |
++                 MT7530_PHY_INDIRECT_ACCESS, MT7530_CHG_TRAP);
+ 
+       if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ)
+               mt7530_pll_setup(priv);
+@@ -2488,8 +2501,11 @@ mt7530_setup(struct dsa_switch *ds)
+                       break;
+               }
+ 
+-              if (priv->p5_mode == MUX_PHY_P0 || priv->p5_mode == MUX_PHY_P4)
++              if (priv->p5_mode == MUX_PHY_P0 ||
++                  priv->p5_mode == MUX_PHY_P4) {
++                      mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS);
+                       mt7530_setup_port5(ds, interface);
++              }
+       }
+ 
+ #ifdef CONFIG_GPIOLIB