ipq40xx: add v5.4 support

[openwrt/staging/blogic.git] / target / linux / ipq40xx / patches-5.4 / 900-dts-ipq4019-ap-dk01.1.patch

diff --git a/target/linux/ipq40xx/patches-5.4/900-dts-ipq4019-ap-dk01.1.patch b/target/linux/ipq40xx/patches-5.4/900-dts-ipq4019-ap-dk01.1.patch
new file mode 100644 (file)
index 0000000..4882537
--- /dev/null
+++ b/target/linux/ipq40xx/patches-5.4/900-dts-ipq4019-ap-dk01.1.patch
@@ -0,0 +1,157 @@
+--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+@@ -15,6 +15,7 @@
+  */
+ 
+ #include "qcom-ipq4019.dtsi"
++#include <dt-bindings/soc/qcom,tcsr.h>
+ 
+ / {
+       model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
+@@ -29,6 +30,32 @@
+       };
+ 
+       soc {
++              tcsr@194b000 {
++                      /* select hostmode */
++                      compatible = "qcom,tcsr";
++                      reg = <0x194b000 0x100>;
++                      qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
++                      status = "ok";
++              };
++
++              ess_tcsr@1953000 {
++                      compatible = "qcom,tcsr";
++                      reg = <0x1953000 0x1000>;
++                      qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
++              };
++
++              tcsr@1949000 {
++                      compatible = "qcom,tcsr";
++                      reg = <0x1949000 0x100>;
++                      qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
++              };
++
++              tcsr@1957000 {
++                      compatible = "qcom,tcsr";
++                      reg = <0x1957000 0x100>;
++                      qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
++              };
++
+               rng@22000 {
+                       status = "ok";
+               };
+@@ -74,14 +101,6 @@
+                       pinctrl-names = "default";
+                       status = "ok";
+                       cs-gpios = <&tlmm 54 0>;
+-
+-                      mx25l25635e@0 {
+-                              #address-cells = <1>;
+-                              #size-cells = <1>;
+-                              reg = <0>;
+-                              compatible = "mx25l25635e";
+-                              spi-max-frequency = <24000000>;
+-                      };
+               };
+ 
+               serial@78af000 {
+@@ -110,6 +129,22 @@
+                       status = "ok";
+               };
+ 
++              mdio@90000 {
++                      status = "okay";
++              };
++
++              ess-switch@c000000 {
++                      status = "okay";
++              };
++
++              ess-psgmii@98000 {
++                      status = "okay";
++              };
++
++              edma@c080000 {
++                      status = "okay";
++              };
++
+               usb3_ss_phy: ssphy@9a000 {
+                       status = "ok";
+               };
+--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
++++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
+@@ -18,5 +18,73 @@
+ 
+ / {
+       model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1";
++      compatible = "qcom,ap-dk01.1-c1", "qcom,ap-dk01.2-c1";
+ 
++      memory {
++              device_type = "memory";
++              reg = <0x80000000 0x10000000>;
++      };
++};
++
++&blsp1_spi1 {
++      mx25l25635f@0 {
++              compatible = "mx25l25635f", "jedec,spi-nor";
++              #address-cells = <1>;
++              #size-cells = <1>;
++              reg = <0>;
++              spi-max-frequency = <24000000>;
++
++              SBL1@0 {
++                      label = "SBL1";
++                      reg = <0x0 0x40000>;
++                      read-only;
++              };
++              MIBIB@40000 {
++                      label = "MIBIB";
++                      reg = <0x40000 0x20000>;
++                      read-only;
++              };
++              QSEE@60000 {
++                      label = "QSEE";
++                      reg = <0x60000 0x60000>;
++                      read-only;
++              };
++              CDT@c0000 {
++                      label = "CDT";
++                      reg = <0xc0000 0x10000>;
++                      read-only;
++              };
++              DDRPARAMS@d0000 {
++                      label = "DDRPARAMS";
++                      reg = <0xd0000 0x10000>;
++                      read-only;
++              };
++              APPSBLENV@e0000 {
++                      label = "APPSBLENV";
++                      reg = <0xe0000 0x10000>;
++                      read-only;
++              };
++              APPSBL@f0000 {
++                      label = "APPSBL";
++                      reg = <0xf0000 0x80000>;
++                      read-only;
++              };
++              ART@170000 {
++                      label = "ART";
++                      reg = <0x170000 0x10000>;
++                      read-only;
++              };
++              kernel@180000 {
++                      label = "kernel";
++                      reg = <0x180000 0x400000>;
++              };
++              rootfs@580000 {
++                      label = "rootfs";
++                      reg = <0x580000 0x1600000>;
++              };
++              firmware@180000 {
++                      label = "firmware";
++                      reg = <0x180000 0x1a00000>;
++              };
++      };
+ };