ipq806x: convert each device to DSA implementation

[openwrt/openwrt.git] / target / linux / ipq806x / files / arch / arm / boot / dts / qcom-ipq8064-eax500.dtsi

diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi
index 3e6732e9df2f52ad92a54fe44b5717baa621cc10..fac43e785fb2eaaad63e3c8829055398cb49b9e7 100644 (file)
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
-#include "qcom-ipq8064-v2.0.dtsi"
+#include "qcom-ipq8064-v2.0-smb208.dtsi"
 
 #include <dt-bindings/input/input.h>
 
@@ -12,10 +12,38 @@
        };
 };
 
+&qcom_pinmux {
+       /* eax500 routers reuse the pcie2 reset pin for switch reset pin */
+       switch_reset: switch_reset_pins {
+               mux {
+                       pins = "gpio63";
+                       function = "gpio";
+                       drive-strength = <12>;
+                       bias-pull-up;
+               };
+       };
+};
+
+&hs_phy_0 {
+       status = "okay";
+};
+
+&ss_phy_0 {
+       status = "okay";
+};
+
 &usb3_0 {
        status = "okay";
 };
 
+&hs_phy_1 {
+       status = "okay";
+};
+
+&ss_phy_1 {
+       status = "okay";
+};
+
 &usb3_1 {
        status = "okay";
 };
@@ -30,15 +58,8 @@
        status = "okay";
 };
 
-&pcie2 {
+&nand {
        status = "okay";
-};
-
-&nand_controller {
-       status = "okay";
-
-       pinctrl-0 = <&nand_pins>;
-       pinctrl-names = "default";
 
        nand@0 {
                reg = <0>;
@@ -48,6 +69,9 @@
                nand-bus-width = <8>;
                nand-ecc-step-size = <512>;
 
+               nand-is-boot-medium;
+               qcom,boot-partitions = <0x0 0x0c80000>;
+
                partitions: partitions {
                        compatible = "fixed-partitions";
                        #address-cells = <1>;
@@ -130,12 +154,12 @@
 
                        partition@f80000 {
                                label = "kernel1";
-                               reg = <0x0f80000 0x2800000>;  /* 3 MB spill to rootfs */
+                               reg = <0x0f80000 0x2800000>;  /* 4 MB, spill to rootfs */
                        };
 
-                       partition@1280000 {
+                       partition@1380000 {
                                label = "rootfs1";
-                               reg = <0x1280000 0x2500000>;
+                               reg = <0x1380000 0x2400000>;
                        };
 
                        partition@3780000 {
@@ -143,9 +167,9 @@
                                reg = <0x3780000 0x2800000>;
                        };
 
-                       partition@3a80000 {
+                       partition@3b80000 {
                                label = "rootfs2";
-                               reg = <0x3a80000 0x2500000>;
+                               reg = <0x3b80000 0x2400000>;
                        };
                };
        };
@@ -157,18 +181,110 @@
        pinctrl-0 = <&mdio0_pins>;
        pinctrl-names = "default";
 
-       phy0: ethernet-phy@0 {
-               reg = <0>;
-               qca,ar8327-initvals = <
-                       0x00004 0x7600000   /* PAD0_MODE */
-                       0x00008 0x1000000   /* PAD5_MODE */
-                       0x0000c 0x80        /* PAD6_MODE */
-                       0x00010 0x2613a0    /* PWS_REG */
-                       0x000e4 0x6a545     /* MAC_POWER_SEL */
-                       0x000e0 0xc74164de  /* SGMII_CTRL */
-                       0x0007c 0x4e        /* PORT0_STATUS */
-                       0x00094 0x4e        /* PORT6_STATUS */
-                       >;
+       /* Switch from documentation require at least 10ms for reset */
+       reset-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_HIGH>;
+       reset-post-delay-us = <12000>;
+
+       switch@10 {
+               compatible = "qca,qca8337";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               reg = <0x10>;
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@0 {
+                               reg = <0>;
+                               label = "cpu";
+                               ethernet = <&gmac1>;
+                               phy-mode = "rgmii";
+                               tx-internal-delay-ps = <1000>;
+                               rx-internal-delay-ps = <1000>;
+
+                               fixed-link {
+                                       speed = <1000>;
+                                       full-duplex;
+                               };
+                       };
+
+                       port@1 {
+                               reg = <1>;
+                               label = "lan1";
+                               phy-mode = "internal";
+                               phy-handle = <&phy_port1>;
+                       };
+
+                       port@2 {
+                               reg = <2>;
+                               label = "lan2";
+                               phy-mode = "internal";
+                               phy-handle = <&phy_port2>;
+                       };
+
+                       port@3 {
+                               reg = <3>;
+                               label = "lan3";
+                               phy-mode = "internal";
+                               phy-handle = <&phy_port3>;
+                       };
+
+                       port@4 {
+                               reg = <4>;
+                               label = "lan4";
+                               phy-mode = "internal";
+                               phy-handle = <&phy_port4>;
+                       };
+
+                       port@5 {
+                               reg = <5>;
+                               label = "wan";
+                               phy-mode = "internal";
+                               phy-handle = <&phy_port5>;
+                       };
+
+                       /*
+                       port@6 {
+                               reg = <0>;
+                               label = "cpu";
+                               ethernet = <&gmac2>;
+                               phy-mode = "rgmii";
+
+                               fixed-link {
+                                       speed = <1000>;
+                                       full-duplex;
+                                       pause;
+                                       asym-pause;
+                               };
+                       };
+                       */
+               };
+
+               mdio {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       phy_port1: phy@0 {
+                               reg = <0>;
+                       };
+
+                       phy_port2: phy@1 {
+                               reg = <1>;
+                       };
+
+                       phy_port3: phy@2 {
+                               reg = <2>;
+                       };
+
+                       phy_port4: phy@3 {
+                               reg = <3>;
+                       };
+
+                       phy_port5: phy@4 {
+                               reg = <4>;
+                       };
+               };
        };
 };