ipq806x: update clk and cpufreq drivers

[openwrt/staging/nbd.git] / target / linux / ipq806x / patches-4.9 / 0038-clk-qcom-Add-support-for-High-Frequency-PLLs-HFPLLs.patch

diff --git a/target/linux/ipq806x/patches-4.9/0038-clk-qcom-Add-support-for-High-Frequency-PLLs-HFPLLs.patch b/target/linux/ipq806x/patches-4.9/0038-clk-qcom-Add-support-for-High-Frequency-PLLs-HFPLLs.patch
index e3797cfb710ca99275ccbe382c5f9f405d00ca67..70926143ec72655ae170e78b8a567a3bb74fa3b6 100644 (file)
--- a/target/linux/ipq806x/patches-4.9/0038-clk-qcom-Add-support-for-High-Frequency-PLLs-HFPLLs.patch
+++ b/target/linux/ipq806x/patches-4.9/0038-clk-qcom-Add-support-for-High-Frequency-PLLs-HFPLLs.patch
@@ -1,7 +1,19 @@
-From f044ffe2d612dcaa2de36c918aaab79c8db1482e Mon Sep 17 00:00:00 2001
+From patchwork Fri Dec  8 09:42:21 2017
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+Subject: [v4,03/12] clk: qcom: Add support for High-Frequency PLLs (HFPLLs)
+From: Sricharan R <sricharan@codeaurora.org>
+X-Patchwork-Id: 10102083
+Message-Id: <1512726150-7204-4-git-send-email-sricharan@codeaurora.org>
+To: mturquette@baylibre.com, sboyd@codeaurora.org,
+ devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
+ linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
+ viresh.kumar@linaro.org, linux-arm-kernel@lists.infradead.org
+Cc: sricharan@codeaurora.org
+Date: Fri,  8 Dec 2017 15:12:21 +0530
+
 From: Stephen Boyd <sboyd@codeaurora.org>
-Date: Fri, 20 Mar 2015 23:45:24 -0700
-Subject: [PATCH 38/69] clk: qcom: Add support for High-Frequency PLLs (HFPLLs)
 
 HFPLLs are the main frequency source for Krait CPU clocks. Add
 support for changing the rate of these PLLs.
@@ -105,7 +117,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
 +       * H/W requires a 5us delay between disabling the bypass and
 +       * de-asserting the reset. Delay 10us just to be safe.
 +       */
-+      udelay(10);
++      usleep_range(10, 100);
 +
 +      /* De-assert active-low PLL reset. */
 +      regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N);
@@ -116,7 +128,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
 +                      regmap_read(regmap, hd->status_reg, &val);
 +              } while (!(val & BIT(hd->lock_bit)));
 +      } else {
-+              udelay(60);
++              usleep_range(60, 100);
 +      }
 +
 +      /* Enable PLL output. */
@@ -151,7 +163,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
 +       * and assert the reset.
 +       */
 +      regmap_update_bits(regmap, hd->mode_reg,
-+                      PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL, 0);
++                         PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL, 0);
 +}
 +
 +static void clk_hfpll_disable(struct clk_hw *hw)
@@ -252,7 +264,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
 +              regmap_read(regmap, hd->status_reg, &status);
 +              if (!(status & BIT(hd->lock_bit))) {
 +                      WARN(1, "HFPLL %s is ON, but not locked!\n",
-+                                      __clk_get_name(hw->clk));
++                           __clk_get_name(hw->clk));
 +                      clk_hfpll_disable(hw);
 +                      __clk_hfpll_init_once(hw);
 +              }