ipq807x: add Qualcomm Atheros IPQ807x target

[openwrt/staging/jow.git] / target / linux / ipq807x / patches-5.15 / 0101-clk-qcom-gcc-ipq8074-rework-nss_port5-6-clock-to-mul.patch

diff --git a/target/linux/ipq807x/patches-5.15/0101-clk-qcom-gcc-ipq8074-rework-nss_port5-6-clock-to-mul.patch b/target/linux/ipq807x/patches-5.15/0101-clk-qcom-gcc-ipq8074-rework-nss_port5-6-clock-to-mul.patch
new file mode 100644 (file)
index 0000000..32fb2d9
--- /dev/null
+++ b/target/linux/ipq807x/patches-5.15/0101-clk-qcom-gcc-ipq8074-rework-nss_port5-6-clock-to-mul.patch
@@ -0,0 +1,129 @@
+From f778553f296792f4d1e8b3552603ad6116ea3eb3 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Thu, 3 Nov 2022 14:49:44 +0100
+Subject: [PATCH] clk: qcom: gcc-ipq8074: rework nss_port5/6 clock to multiple
+ conf
+
+Rework nss_port5/6 to use the new multiple configuration implementation
+and correctly fix the clocks for these port under some corner case.
+
+This is particularly relevant for device that have 2.5G or 10G port
+connected to port5 or port 6 on ipq8074. As the parent are shared
+across multiple port it may be required to select the correct
+configuration to accomplish the desired clock. Without this patch such
+port doesn't work in some specific ethernet speed as the clock will be
+set to the wrong frequency as we just select the first configuration for
+the related frequency instead of selecting the best one.
+
+Tested-by: Robert Marko <robimarko@gmail.com> # ipq8074 Qnap QHora-301W
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ drivers/clk/qcom/gcc-ipq8074.c | 64 +++++++++++++++++++++++++---------
+ 1 file changed, 48 insertions(+), 16 deletions(-)
+
+--- a/drivers/clk/qcom/gcc-ipq8074.c
++++ b/drivers/clk/qcom/gcc-ipq8074.c
+@@ -1682,13 +1682,21 @@ static struct clk_regmap_div nss_port4_t
+       },
+ };
+ 
++static const struct freq_conf ftbl_nss_port5_rx_clk_src_25[] = {
++      C(P_UNIPHY1_RX, 12.5, 0, 0),
++      C(P_UNIPHY0_RX, 5, 0, 0),
++};
++
++static const struct freq_conf ftbl_nss_port5_rx_clk_src_125[] = {
++      C(P_UNIPHY1_RX, 2.5, 0, 0),
++      C(P_UNIPHY0_RX, 1, 0, 0),
++};
++
+ static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
+       F(19200000, P_XO, 1, 0, 0),
+-      F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
+-      F(25000000, P_UNIPHY0_RX, 5, 0, 0),
++      FM(25000000, ftbl_nss_port5_rx_clk_src_25),
+       F(78125000, P_UNIPHY1_RX, 4, 0, 0),
+-      F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
+-      F(125000000, P_UNIPHY0_RX, 1, 0, 0),
++      FM(125000000, ftbl_nss_port5_rx_clk_src_125),
+       F(156250000, P_UNIPHY1_RX, 2, 0, 0),
+       F(312500000, P_UNIPHY1_RX, 1, 0, 0),
+       { }
+@@ -1744,13 +1752,21 @@ static struct clk_regmap_div nss_port5_r
+       },
+ };
+ 
++static struct freq_conf ftbl_nss_port5_tx_clk_src_25[] = {
++      C(P_UNIPHY1_TX, 12.5, 0, 0),
++      C(P_UNIPHY0_TX, 5, 0, 0),
++};
++
++static struct freq_conf ftbl_nss_port5_tx_clk_src_125[] = {
++      C(P_UNIPHY1_TX, 2.5, 0, 0),
++      C(P_UNIPHY0_TX, 1, 0, 0),
++};
++
+ static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
+       F(19200000, P_XO, 1, 0, 0),
+-      F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
+-      F(25000000, P_UNIPHY0_TX, 5, 0, 0),
++      FM(25000000, ftbl_nss_port5_tx_clk_src_25),
+       F(78125000, P_UNIPHY1_TX, 4, 0, 0),
+-      F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
+-      F(125000000, P_UNIPHY0_TX, 1, 0, 0),
++      FM(125000000, ftbl_nss_port5_tx_clk_src_125),
+       F(156250000, P_UNIPHY1_TX, 2, 0, 0),
+       F(312500000, P_UNIPHY1_TX, 1, 0, 0),
+       { }
+@@ -1806,13 +1822,21 @@ static struct clk_regmap_div nss_port5_t
+       },
+ };
+ 
++static struct freq_conf ftbl_nss_port6_rx_clk_src_25[] = {
++      C(P_UNIPHY2_RX, 5, 0, 0),
++      C(P_UNIPHY2_RX, 12.5, 0, 0),
++};
++
++static struct freq_conf ftbl_nss_port6_rx_clk_src_125[] = {
++      C(P_UNIPHY2_RX, 1, 0, 0),
++      C(P_UNIPHY2_RX, 2.5, 0, 0),
++};
++
+ static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = {
+       F(19200000, P_XO, 1, 0, 0),
+-      F(25000000, P_UNIPHY2_RX, 5, 0, 0),
+-      F(25000000, P_UNIPHY2_RX, 12.5, 0, 0),
++      FM(25000000, ftbl_nss_port6_rx_clk_src_25),
+       F(78125000, P_UNIPHY2_RX, 4, 0, 0),
+-      F(125000000, P_UNIPHY2_RX, 1, 0, 0),
+-      F(125000000, P_UNIPHY2_RX, 2.5, 0, 0),
++      FM(125000000, ftbl_nss_port6_rx_clk_src_125),
+       F(156250000, P_UNIPHY2_RX, 2, 0, 0),
+       F(312500000, P_UNIPHY2_RX, 1, 0, 0),
+       { }
+@@ -1863,13 +1887,21 @@ static struct clk_regmap_div nss_port6_r
+       },
+ };
+ 
++static struct freq_conf ftbl_nss_port6_tx_clk_src_25[] = {
++      C(P_UNIPHY2_TX, 5, 0, 0),
++      C(P_UNIPHY2_TX, 12.5, 0, 0),
++};
++
++static struct freq_conf ftbl_nss_port6_tx_clk_src_125[] = {
++      C(P_UNIPHY2_TX, 1, 0, 0),
++      C(P_UNIPHY2_TX, 2.5, 0, 0),
++};
++
+ static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = {
+       F(19200000, P_XO, 1, 0, 0),
+-      F(25000000, P_UNIPHY2_TX, 5, 0, 0),
+-      F(25000000, P_UNIPHY2_TX, 12.5, 0, 0),
++      FM(25000000, ftbl_nss_port6_tx_clk_src_25),
+       F(78125000, P_UNIPHY2_TX, 4, 0, 0),
+-      F(125000000, P_UNIPHY2_TX, 1, 0, 0),
+-      F(125000000, P_UNIPHY2_TX, 2.5, 0, 0),
++      FM(125000000, ftbl_nss_port6_tx_clk_src_125),
+       F(156250000, P_UNIPHY2_TX, 2, 0, 0),
+       F(312500000, P_UNIPHY2_TX, 1, 0, 0),
+       { }