ipq807x: renumber upstreamed patches

[openwrt/staging/jow.git] / target / linux / ipq807x / patches-6.1 / 0017-v6.2-arm64-dts-qcom-ipq8074-align-TLMM-pin-configuration-.patch

diff --git a/target/linux/ipq807x/patches-6.1/0017-v6.2-arm64-dts-qcom-ipq8074-align-TLMM-pin-configuration-.patch b/target/linux/ipq807x/patches-6.1/0017-v6.2-arm64-dts-qcom-ipq8074-align-TLMM-pin-configuration-.patch
new file mode 100644 (file)
index 0000000..1ce1140
--- /dev/null
+++ b/target/linux/ipq807x/patches-6.1/0017-v6.2-arm64-dts-qcom-ipq8074-align-TLMM-pin-configuration-.patch
@@ -0,0 +1,60 @@
+From 5f20690f77878b1ba24ec88df01b92d5131a6780 Mon Sep 17 00:00:00 2001
+From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Date: Tue, 8 Nov 2022 15:23:57 +0100
+Subject: [PATCH] arm64: dts: qcom: ipq8074: align TLMM pin configuration with
+ DT schema
+
+DT schema expects TLMM pin configuration nodes to be named with
+'-state' suffix and their optional children with '-pins' suffix.
+
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20221108142357.67202-2-krzysztof.kozlowski@linaro.org
+---
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -318,35 +318,35 @@
+                       interrupt-controller;
+                       #interrupt-cells = <0x2>;
+ 
+-                      serial_4_pins: serial4-pinmux {
++                      serial_4_pins: serial4-state {
+                               pins = "gpio23", "gpio24";
+                               function = "blsp4_uart1";
+                               drive-strength = <8>;
+                               bias-disable;
+                       };
+ 
+-                      i2c_0_pins: i2c-0-pinmux {
++                      i2c_0_pins: i2c-0-state {
+                               pins = "gpio42", "gpio43";
+                               function = "blsp1_i2c";
+                               drive-strength = <8>;
+                               bias-disable;
+                       };
+ 
+-                      spi_0_pins: spi-0-pins {
++                      spi_0_pins: spi-0-state {
+                               pins = "gpio38", "gpio39", "gpio40", "gpio41";
+                               function = "blsp0_spi";
+                               drive-strength = <8>;
+                               bias-disable;
+                       };
+ 
+-                      hsuart_pins: hsuart-pins {
++                      hsuart_pins: hsuart-state {
+                               pins = "gpio46", "gpio47", "gpio48", "gpio49";
+                               function = "blsp2_uart";
+                               drive-strength = <8>;
+                               bias-disable;
+                       };
+ 
+-                      qpic_pins: qpic-pins {
++                      qpic_pins: qpic-state {
+                               pins = "gpio1", "gpio3", "gpio4",
+                                      "gpio5", "gpio6", "gpio7",
+                                      "gpio8", "gpio10", "gpio11",