ipq807x: renumber upstreamed patches

[openwrt/openwrt.git] / target / linux / ipq807x / patches-6.1 / 0052-v6.2-clk-qcom-ipq8074-populate-fw_name-for-all-parents.patch

diff --git a/target/linux/ipq807x/patches-6.1/0052-v6.2-clk-qcom-ipq8074-populate-fw_name-for-all-parents.patch b/target/linux/ipq807x/patches-6.1/0052-v6.2-clk-qcom-ipq8074-populate-fw_name-for-all-parents.patch
deleted file mode 100644 (file)
index 7372b1d..0000000
--- a/target/linux/ipq807x/patches-6.1/0052-v6.2-clk-qcom-ipq8074-populate-fw_name-for-all-parents.patch
+++ /dev/null
@@ -1,152 +0,0 @@
-From 78936d46470938caa9a7ea529deeb36777b4f98e Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Wed, 16 Nov 2022 22:46:55 +0100
-Subject: [PATCH] clk: qcom: ipq8074: populate fw_name for all parents
-
-It appears that having only .name populated in parent_data for clocks
-which are only globally searchable currently will not work as the clk core
-won't copy that name if there is no .fw_name present as well.
-
-So, populate .fw_name for all parent clocks in parent_data.
-
-Fixes: ae55ad32e273 ("clk: qcom: ipq8074: convert to parent data")
-
-Co-developed-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221116214655.1116467-1-robimarko@gmail.com
----
- drivers/clk/qcom/gcc-ipq8074.c | 52 +++++++++++++++++-----------------
- 1 file changed, 26 insertions(+), 26 deletions(-)
-
---- a/drivers/clk/qcom/gcc-ipq8074.c
-+++ b/drivers/clk/qcom/gcc-ipq8074.c
-@@ -680,7 +680,7 @@ static struct clk_rcg2 pcie0_aux_clk_src
- };
- 
- static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
--      { .name = "pcie20_phy0_pipe_clk" },
-+      { .fw_name = "pcie0_pipe", .name = "pcie20_phy0_pipe_clk" },
-       { .fw_name = "xo", .name = "xo" },
- };
- 
-@@ -733,7 +733,7 @@ static struct clk_rcg2 pcie1_aux_clk_src
- };
- 
- static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = {
--      { .name = "pcie20_phy1_pipe_clk" },
-+      { .fw_name = "pcie1_pipe", .name = "pcie20_phy1_pipe_clk" },
-       { .fw_name = "xo", .name = "xo" },
- };
- 
-@@ -1137,7 +1137,7 @@ static const struct freq_tbl ftbl_nss_no
- 
- static const struct clk_parent_data gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
-       { .fw_name = "xo", .name = "xo" },
--      { .name = "bias_pll_nss_noc_clk" },
-+      { .fw_name = "bias_pll_nss_noc_clk", .name = "bias_pll_nss_noc_clk" },
-       { .hw = &gpll0.clkr.hw },
-       { .hw = &gpll2.clkr.hw },
- };
-@@ -1362,7 +1362,7 @@ static const struct freq_tbl ftbl_nss_pp
- 
- static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
-       { .fw_name = "xo", .name = "xo" },
--      { .name = "bias_pll_cc_clk" },
-+      { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
-       { .hw = &gpll0.clkr.hw },
-       { .hw = &gpll4.clkr.hw },
-       { .hw = &nss_crypto_pll.clkr.hw },
-@@ -1413,10 +1413,10 @@ static const struct freq_tbl ftbl_nss_po
- 
- static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
-       { .fw_name = "xo", .name = "xo" },
--      { .name = "uniphy0_gcc_rx_clk" },
--      { .name = "uniphy0_gcc_tx_clk" },
-+      { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
-+      { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
-       { .hw = &ubi32_pll.clkr.hw },
--      { .name = "bias_pll_cc_clk" },
-+      { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
- };
- 
- static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
-@@ -1465,10 +1465,10 @@ static const struct freq_tbl ftbl_nss_po
- 
- static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
-       { .fw_name = "xo", .name = "xo" },
--      { .name = "uniphy0_gcc_tx_clk" },
--      { .name = "uniphy0_gcc_rx_clk" },
-+      { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
-+      { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
-       { .hw = &ubi32_pll.clkr.hw },
--      { .name = "bias_pll_cc_clk" },
-+      { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
- };
- 
- static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
-@@ -1696,12 +1696,12 @@ static const struct freq_tbl ftbl_nss_po
- 
- static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
-       { .fw_name = "xo", .name = "xo" },
--      { .name = "uniphy0_gcc_rx_clk" },
--      { .name = "uniphy0_gcc_tx_clk" },
--      { .name = "uniphy1_gcc_rx_clk" },
--      { .name = "uniphy1_gcc_tx_clk" },
-+      { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
-+      { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
-+      { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
-+      { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
-       { .hw = &ubi32_pll.clkr.hw },
--      { .name = "bias_pll_cc_clk" },
-+      { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
- };
- 
- static const struct parent_map
-@@ -1758,12 +1758,12 @@ static const struct freq_tbl ftbl_nss_po
- 
- static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
-       { .fw_name = "xo", .name = "xo" },
--      { .name = "uniphy0_gcc_tx_clk" },
--      { .name = "uniphy0_gcc_rx_clk" },
--      { .name = "uniphy1_gcc_tx_clk" },
--      { .name = "uniphy1_gcc_rx_clk" },
-+      { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
-+      { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
-+      { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
-+      { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
-       { .hw = &ubi32_pll.clkr.hw },
--      { .name = "bias_pll_cc_clk" },
-+      { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
- };
- 
- static const struct parent_map
-@@ -1820,10 +1820,10 @@ static const struct freq_tbl ftbl_nss_po
- 
- static const struct clk_parent_data gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
-       { .fw_name = "xo", .name = "xo" },
--      { .name = "uniphy2_gcc_rx_clk" },
--      { .name = "uniphy2_gcc_tx_clk" },
-+      { .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
-+      { .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
-       { .hw = &ubi32_pll.clkr.hw },
--      { .name = "bias_pll_cc_clk" },
-+      { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
- };
- 
- static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
-@@ -1877,10 +1877,10 @@ static const struct freq_tbl ftbl_nss_po
- 
- static const struct clk_parent_data gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
-       { .fw_name = "xo", .name = "xo" },
--      { .name = "uniphy2_gcc_tx_clk" },
--      { .name = "uniphy2_gcc_rx_clk" },
-+      { .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
-+      { .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
-       { .hw = &ubi32_pll.clkr.hw },
--      { .name = "bias_pll_cc_clk" },
-+      { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
- };
- 
- static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {