ixp4xx: Bump to kernel v6.6

[openwrt/staging/nbd.git] / target / linux / ixp4xx / patches-6.6 / 0004-ARM-dts-usr8200-Fix-phy-registers.patch

diff --git a/target/linux/ixp4xx/patches-6.6/0004-ARM-dts-usr8200-Fix-phy-registers.patch b/target/linux/ixp4xx/patches-6.6/0004-ARM-dts-usr8200-Fix-phy-registers.patch
new file mode 100644 (file)
index 0000000..93458bc
--- /dev/null
+++ b/target/linux/ixp4xx/patches-6.6/0004-ARM-dts-usr8200-Fix-phy-registers.patch
@@ -0,0 +1,69 @@
+From 98f3b5f44b9ae86c4a80185b57149867472a2570 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 20 Oct 2023 15:11:41 +0200
+Subject: [PATCH] ARM: dts: usr8200: Fix phy registers
+
+The MV88E6060 switch has internal PHY registers at MDIO
+addresses 0x00..0x04. Tie each port to the corresponding
+PHY.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Link: https://lore.kernel.org/r/20231020-ixp4xx-usr8200-dtsfix-v1-1-3a8591dea259@linaro.org
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+---
+ .../ixp/intel-ixp42x-usrobotics-usr8200.dts   | 22 +++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts
++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts
+@@ -165,6 +165,24 @@
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+ 
++                              /*
++                               * PHY 0..4 are internal to the MV88E6060 switch but appear
++                               * as independent devices.
++                               */
++                              phy0: ethernet-phy@0 {
++                                      reg = <0>;
++                              };
++                              phy1: ethernet-phy@1 {
++                                      reg = <1>;
++                              };
++                              phy2: ethernet-phy@2 {
++                                      reg = <2>;
++                              };
++                              phy3: ethernet-phy@3 {
++                                      reg = <3>;
++                              };
++
++                              /* Altima AMI101L used by the WAN port */
+                               phy9: ethernet-phy@9 {
+                                       reg = <9>;
+                               };
+@@ -181,21 +199,25 @@
+                                               port@0 {
+                                                       reg = <0>;
+                                                       label = "lan1";
++                                                      phy-handle = <&phy0>;
+                                               };
+ 
+                                               port@1 {
+                                                       reg = <1>;
+                                                       label = "lan2";
++                                                      phy-handle = <&phy1>;
+                                               };
+ 
+                                               port@2 {
+                                                       reg = <2>;
+                                                       label = "lan3";
++                                                      phy-handle = <&phy2>;
+                                               };
+ 
+                                               port@3 {
+                                                       reg = <3>;
+                                                       label = "lan4";
++                                                      phy-handle = <&phy3>;
+                                               };
+ 
+                                               port@5 {