jh71x0: refresh patches and configs once again

[openwrt/staging/wigyori.git] / target / linux / jh71x0 / patches-6.1 / 0033-dt-bindings-clock-jh7110-syscrg-Add-PLL-clock-inputs.patch

diff --git a/target/linux/jh71x0/patches-6.1/0033-dt-bindings-clock-jh7110-syscrg-Add-PLL-clock-inputs.patch b/target/linux/jh71x0/patches-6.1/0033-dt-bindings-clock-jh7110-syscrg-Add-PLL-clock-inputs.patch
index da637d375dbe164e726000debf149cc8689dbb5b..a1f200936ef429dfe4779e258d40768dcb71ab97 100644 (file)
--- a/target/linux/jh71x0/patches-6.1/0033-dt-bindings-clock-jh7110-syscrg-Add-PLL-clock-inputs.patch
+++ b/target/linux/jh71x0/patches-6.1/0033-dt-bindings-clock-jh7110-syscrg-Add-PLL-clock-inputs.patch
@@ -1,7 +1,7 @@
-From a8b8cf31c3802978b35b96bf1e051a2d6083ffac Mon Sep 17 00:00:00 2001
+From 1f788a0a5092b1e1cfd02aa7f31ceb551befa7e6 Mon Sep 17 00:00:00 2001
 From: Xingyu Wu <xingyu.wu@starfivetech.com>
 Date: Tue, 14 Mar 2023 16:43:50 +0800
-Subject: [PATCH 033/129] dt-bindings: clock: jh7110-syscrg: Add PLL clock
+Subject: [PATCH 033/122] dt-bindings: clock: jh7110-syscrg: Add PLL clock
  inputs
 
 Add PLL clock inputs from PLL clock generator.
@@ -13,7 +13,7 @@ Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
  1 file changed, 18 insertions(+), 2 deletions(-)
 
 diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
-index 84373ae31..55d4e7f09 100644
+index 84373ae31644..55d4e7f09cd5 100644
 --- a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
 +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
 @@ -27,6 +27,9 @@ properties:
@@ -76,5 +76,5 @@ index 84373ae31..55d4e7f09 100644
          #reset-cells = <1>;
      };
 -- 
-2.25.1
+2.20.1