jh71x0: add new target for StarFive JH7100/7110 SoC
[openwrt/staging/wigyori.git] / target / linux / jh71x0 / patches-6.1 / 0075-dt-bindings-usb-Add-StarFive-JH7110-USB-controller.patch
diff --git a/target/linux/jh71x0/patches-6.1/0075-dt-bindings-usb-Add-StarFive-JH7110-USB-controller.patch b/target/linux/jh71x0/patches-6.1/0075-dt-bindings-usb-Add-StarFive-JH7110-USB-controller.patch
new file mode 100644 (file)
index 0000000..0c606b2
--- /dev/null
@@ -0,0 +1,157 @@
+From ca6592878708d1cc045c55e846cfe6baaf0be06c Mon Sep 17 00:00:00 2001
+From: Minda Chen <minda.chen@starfivetech.com>
+Date: Thu, 20 Apr 2023 19:00:50 +0800
+Subject: [PATCH 75/95] dt-bindings: usb: Add StarFive JH7110 USB controller
+
+StarFive JH7110 platforms USB have a wrapper module around
+the Cadence USBSS-DRD controller. Add binding information doc
+for that.
+
+Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
+Reviewed-by: Peter Chen <peter.chen@kernel.org>
+Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
+---
+ .../bindings/usb/starfive,jh7110-usb.yaml     | 131 ++++++++++++++++++
+ 1 file changed, 131 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
+
+diff --git a/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
+new file mode 100644
+index 000000000000..e6bd8a583da3
+--- /dev/null
++++ b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
+@@ -0,0 +1,131 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/usb/starfive,jh7110-usb.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: StarFive JH7110 Cadence USBSS-DRD SoC controller
++
++maintainers:
++  - Minda Chen <minda.chen@starfivetech.com>
++
++properties:
++  compatible:
++    const: starfive,jh7110-usb
++
++  reg:
++    items:
++      - description: OTG controller registers
++      - description: XHCI Host controller registers
++      - description: DEVICE controller registers
++
++  reg-names:
++    items:
++      - const: otg
++      - const: xhci
++      - const: dev
++
++  interrupts:
++    items:
++      - description: XHCI host controller interrupt
++      - description: Device controller interrupt
++      - description: OTG/DRD controller interrupt
++
++  interrupt-names:
++    items:
++      - const: host
++      - const: peripheral
++      - const: otg
++
++  clocks:
++    items:
++      - description: low power clock
++      - description: STB clock
++      - description: APB clock
++      - description: AXI clock
++      - description: UTMI APB clock
++
++  clock-names:
++    items:
++      - const: lpm
++      - const: stb
++      - const: apb
++      - const: axi
++      - const: utmi_apb
++
++  resets:
++    items:
++      - description: Power up reset
++      - description: APB clock reset
++      - description: AXI clock reset
++      - description: UTMI APB clock reset
++
++  reset-names:
++    items:
++      - const: pwrup
++      - const: apb
++      - const: axi
++      - const: utmi_apb
++
++  starfive,stg-syscon:
++    $ref: /schemas/types.yaml#/definitions/phandle-array
++    items:
++      -  items:
++           - description: phandle to System Register Controller stg_syscon node.
++           - description: dr mode register offset of STG_SYSCONSAIF__SYSCFG register for USB.
++    description:
++      The phandle to System Register Controller syscon node and the offset
++      of STG_SYSCONSAIF__SYSCFG register for USB.
++
++  dr_mode:
++    enum: [host, otg, peripheral]
++
++  phys:
++    minItems: 1
++    maxItems: 2
++
++  phy-names:
++    minItems: 1
++    maxItems: 2
++    items:
++      anyOf:
++        - const: usb2
++        - const: usb3
++
++required:
++  - compatible
++  - reg
++  - reg-names
++  - interrupts
++  - interrupt-names
++  - clocks
++  - resets
++  - starfive,stg-syscon
++  - dr_mode
++
++additionalProperties: false
++
++examples:
++  - |
++    usb@10100000 {
++        compatible = "starfive,jh7110-usb";
++        reg = <0x10100000 0x10000>,
++              <0x10110000 0x10000>,
++              <0x10120000 0x10000>;
++        reg-names = "otg", "xhci", "dev";
++        interrupts = <100>, <108>, <110>;
++        interrupt-names = "host", "peripheral", "otg";
++        clocks = <&syscrg 4>,
++                 <&stgcrg 5>,
++                 <&stgcrg 1>,
++                 <&stgcrg 3>,
++                 <&stgcrg 2>;
++        clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
++        resets = <&stgcrg 10>,
++                 <&stgcrg 8>,
++                 <&stgcrg 7>,
++                 <&stgcrg 9>;
++        reset-names = "pwrup", "apb", "axi", "utmi_apb";
++        starfive,stg-syscon = <&stg_syscon 0x4>;
++        dr_mode = "host";
++    };
+-- 
+2.20.1
+