+++ /dev/null
-From 84707813ac114be80eb31244916f3e0bdd3ed15b Mon Sep 17 00:00:00 2001
-From: William Qiu <william.qiu@starfivetech.com>
-Date: Fri, 12 May 2023 10:20:35 +0800
-Subject: [PATCH 87/95] riscv: dts: starfive: jh7110: Add syscon nodes
-
-Add stg_syscon/sys_syscon/aon_syscon nodes for JH7110 Soc.
-
-Co-developed-by: Xingyu Wu <xingyu.wu@starfivetech.com>
-Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
-Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
-Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
-Signed-off-by: William Qiu <william.qiu@starfivetech.com>
----
- arch/riscv/boot/dts/starfive/jh7110.dtsi | 16 ++++++++++++++++
- 1 file changed, 16 insertions(+)
-
-diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
-index b6a023b4c23e..d87181cfc09c 100644
---- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
-+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
-@@ -429,6 +429,11 @@
- #reset-cells = <1>;
- };
-
-+ stg_syscon: syscon@10240000 {
-+ compatible = "starfive,jh7110-stg-syscon", "syscon";
-+ reg = <0x0 0x10240000 0x0 0x1000>;
-+ };
-+
- uart3: serial@12000000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x0 0x12000000 0x0 0x10000>;
-@@ -548,6 +553,11 @@
- reg = <0x0 0x13030000 0x0 0x1000>;
- };
-
-+ sys_syscon: syscon@13030000 {
-+ compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
-+ reg = <0x0 0x13030000 0x0 0x1000>;
-+ };
-+
- sysgpio: pinctrl@13040000 {
- compatible = "starfive,jh7110-sys-pinctrl";
- reg = <0x0 0x13040000 0x0 0x10000>;
-@@ -577,6 +587,12 @@
- #reset-cells = <1>;
- };
-
-+ aon_syscon: syscon@17010000 {
-+ compatible = "starfive,jh7110-aon-syscon", "syscon";
-+ reg = <0x0 0x17010000 0x0 0x1000>;
-+ #power-domain-cells = <1>;
-+ };
-+
- aongpio: pinctrl@17020000 {
- compatible = "starfive,jh7110-aon-pinctrl";
- reg = <0x0 0x17020000 0x0 0x10000>;
---
-2.20.1
-