jh71x0: add new target for StarFive JH7100/7110 SoC

[openwrt/staging/wigyori.git] / target / linux / jh71x0 / patches-6.1 / 0091-riscv-dts-starfive-jh7110-Add-ethernet-device-nodes.patch

diff --git a/target/linux/jh71x0/patches-6.1/0091-riscv-dts-starfive-jh7110-Add-ethernet-device-nodes.patch b/target/linux/jh71x0/patches-6.1/0091-riscv-dts-starfive-jh7110-Add-ethernet-device-nodes.patch
new file mode 100644 (file)
index 0000000..b231daa
--- /dev/null
+++ b/target/linux/jh71x0/patches-6.1/0091-riscv-dts-starfive-jh7110-Add-ethernet-device-nodes.patch
@@ -0,0 +1,125 @@
+From 8cce344efbddfcea37a001ce67a652aac02a80d3 Mon Sep 17 00:00:00 2001
+From: Samin Guo <samin.guo@starfivetech.com>
+Date: Fri, 3 Mar 2023 16:49:31 +0800
+Subject: [PATCH 91/95] riscv: dts: starfive: jh7110: Add ethernet device nodes
+
+Add JH7110 ethernet device node to support gmac driver for the JH7110
+RISC-V SoC.
+
+Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
+Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
+---
+ arch/riscv/boot/dts/starfive/jh7110.dtsi | 91 ++++++++++++++++++++++++
+ 1 file changed, 91 insertions(+)
+
+diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
+index 0fb22d4a860e..a9e02c88569a 100644
+--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
++++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
+@@ -243,6 +243,13 @@
+               #clock-cells = <0>;
+       };
+ 
++      stmmac_axi_setup: stmmac-axi-config {
++              snps,lpi_en;
++              snps,wr_osr_lmt = <4>;
++              snps,rd_osr_lmt = <4>;
++              snps,blen = <256 128 64 32 0 0 0>;
++      };
++
+       tdm_ext: tdm-ext-clock {
+               compatible = "fixed-clock";
+               clock-output-names = "tdm_ext";
+@@ -682,5 +689,89 @@
+                       #reset-cells = <1>;
+                       power-domains = <&pwrc JH7110_PD_VOUT>;
+               };
++
++              gmac0: ethernet@16030000 {
++                      compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
++                      reg = <0x0 0x16030000 0x0 0x10000>;
++                      clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>,
++                               <&aoncrg JH7110_AONCLK_GMAC0_AHB>,
++                               <&syscrg JH7110_SYSCLK_GMAC0_PTP>,
++                               <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>,
++                               <&syscrg JH7110_SYSCLK_GMAC0_GTXC>;
++                      clock-names = "stmmaceth", "pclk", "ptp_ref",
++                                    "tx", "gtx";
++                      resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>,
++                               <&aoncrg JH7110_AONRST_GMAC0_AHB>;
++                      reset-names = "stmmaceth", "ahb";
++                      interrupts = <7>, <6>, <5>;
++                      interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
++                      phy-mode = "rgmii-id";
++                      snps,multicast-filter-bins = <64>;
++                      snps,perfect-filter-entries = <8>;
++                      rx-fifo-depth = <2048>;
++                      tx-fifo-depth = <2048>;
++                      snps,fixed-burst;
++                      snps,no-pbl-x8;
++                      snps,force_thresh_dma_mode;
++                      snps,axi-config = <&stmmac_axi_setup>;
++                      snps,tso;
++                      snps,en-tx-lpi-clockgating;
++                      snps,txpbl = <16>;
++                      snps,rxpbl = <16>;
++                      status = "disabled";
++                      phy-handle = <&phy0>;
++
++                      mdio {
++                              #address-cells = <1>;
++                              #size-cells = <0>;
++                              compatible = "snps,dwmac-mdio";
++
++                              phy0: ethernet-phy@0 {
++                                      reg = <0>;
++                              };
++                      };
++              };
++
++              gmac1: ethernet@16040000 {
++                      compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
++                      reg = <0x0 0x16040000 0x0 0x10000>;
++                      clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>,
++                               <&syscrg JH7110_SYSCLK_GMAC1_AHB>,
++                               <&syscrg JH7110_SYSCLK_GMAC1_PTP>,
++                               <&syscrg JH7110_SYSCLK_GMAC1_TX_INV>,
++                               <&syscrg JH7110_SYSCLK_GMAC1_GTXC>;
++                      clock-names = "stmmaceth", "pclk", "ptp_ref",
++                                    "tx", "gtx";
++                      resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>,
++                               <&syscrg JH7110_SYSRST_GMAC1_AHB>;
++                      reset-names = "stmmaceth", "ahb";
++                      interrupts = <78>, <77>, <76>;
++                      interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
++                      phy-mode = "rgmii-id";
++                      snps,multicast-filter-bins = <64>;
++                      snps,perfect-filter-entries = <8>;
++                      rx-fifo-depth = <2048>;
++                      tx-fifo-depth = <2048>;
++                      snps,fixed-burst;
++                      snps,no-pbl-x8;
++                      snps,force_thresh_dma_mode;
++                      snps,axi-config = <&stmmac_axi_setup>;
++                      snps,tso;
++                      snps,en-tx-lpi-clockgating;
++                      snps,txpbl = <16>;
++                      snps,rxpbl = <16>;
++                      status = "disabled";
++                      phy-handle = <&phy1>;
++
++                      mdio {
++                              #address-cells = <1>;
++                              #size-cells = <0>;
++                              compatible = "snps,dwmac-mdio";
++
++                              phy1: ethernet-phy@1 {
++                                      reg = <0>;
++                              };
++                      };
++              };
+       };
+ };
+-- 
+2.20.1
+