jh71x0: update patches and config

[openwrt/staging/wigyori.git] / target / linux / jh71x0 / patches-6.1 / 0092-media-cadence-Add-support-for-external-dphy.patch

diff --git a/target/linux/jh71x0/patches-6.1/0092-media-cadence-Add-support-for-external-dphy.patch b/target/linux/jh71x0/patches-6.1/0092-media-cadence-Add-support-for-external-dphy.patch
new file mode 100644 (file)
index 0000000..1cc53df
--- /dev/null
+++ b/target/linux/jh71x0/patches-6.1/0092-media-cadence-Add-support-for-external-dphy.patch
@@ -0,0 +1,146 @@
+From d5961c9c17fb345b7fa345c0c006e2e8eb8535fa Mon Sep 17 00:00:00 2001
+From: Jack Zhu <jack.zhu@starfivetech.com>
+Date: Tue, 23 May 2023 16:56:25 +0800
+Subject: [PATCH 092/129] media: cadence: Add support for external dphy
+
+Add support for external MIPI D-PHY.
+
+Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
+---
+ drivers/media/platform/cadence/cdns-csi2rx.c | 66 +++++++++++++++++---
+ 1 file changed, 56 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c
+index 1710da5cf..3528cfaf5 100644
+--- a/drivers/media/platform/cadence/cdns-csi2rx.c
++++ b/drivers/media/platform/cadence/cdns-csi2rx.c
+@@ -31,6 +31,12 @@
+ #define CSI2RX_STATIC_CFG_DLANE_MAP(llane, plane)     ((plane) << (16 + (llane) * 4))
+ #define CSI2RX_STATIC_CFG_LANES_MASK                  GENMASK(11, 8)
+ 
++#define CSI2RX_DPHY_LANE_CTRL_REG             0x40
++#define CSI2RX_DPHY_CL_RST                    BIT(16)
++#define CSI2RX_DPHY_DL_RST(i)                 BIT((i) + 12)
++#define CSI2RX_DPHY_CL_EN                     BIT(4)
++#define CSI2RX_DPHY_DL_EN(i)                  BIT(i)
++
+ #define CSI2RX_STREAM_BASE(n)         (((n) + 1) * 0x100)
+ 
+ #define CSI2RX_STREAM_CTRL_REG(n)             (CSI2RX_STREAM_BASE(n) + 0x000)
+@@ -105,6 +111,24 @@ static void csi2rx_reset(struct csi2rx_priv *csi2rx)
+       writel(0, csi2rx->base + CSI2RX_SOFT_RESET_REG);
+ }
+ 
++static int csi2rx_configure_ext_dphy(struct csi2rx_priv *csi2rx)
++{
++      union phy_configure_opts opts = { };
++      int ret;
++
++      ret = phy_power_on(csi2rx->dphy);
++      if (ret)
++              return ret;
++
++      ret = phy_configure(csi2rx->dphy, &opts);
++      if (ret) {
++              phy_power_off(csi2rx->dphy);
++              return ret;
++      }
++
++      return 0;
++}
++
+ static int csi2rx_start(struct csi2rx_priv *csi2rx)
+ {
+       unsigned int i;
+@@ -144,6 +168,17 @@ static int csi2rx_start(struct csi2rx_priv *csi2rx)
+       if (ret)
+               goto err_disable_pclk;
+ 
++      /* Enable DPHY clk and data lanes. */
++      if (csi2rx->dphy) {
++              reg = CSI2RX_DPHY_CL_EN | CSI2RX_DPHY_CL_RST;
++              for (i = 0; i < csi2rx->num_lanes; i++) {
++                      reg |= CSI2RX_DPHY_DL_EN(csi2rx->lanes[i] - 1);
++                      reg |= CSI2RX_DPHY_DL_RST(csi2rx->lanes[i] - 1);
++              }
++
++              writel(reg, csi2rx->base + CSI2RX_DPHY_LANE_CTRL_REG);
++      }
++
+       /*
+        * Create a static mapping between the CSI virtual channels
+        * and the output stream.
+@@ -177,10 +212,22 @@ static int csi2rx_start(struct csi2rx_priv *csi2rx)
+               goto err_disable_pixclk;
+ 
+       reset_control_deassert(csi2rx->sys_rst);
++
++      if (csi2rx->dphy) {
++              ret = csi2rx_configure_ext_dphy(csi2rx);
++              if (ret) {
++                      dev_err(csi2rx->dev,
++                              "Failed to configure external DPHY: %d\n", ret);
++                      goto err_disable_sysclk;
++              }
++      }
++
+       clk_disable_unprepare(csi2rx->p_clk);
+ 
+       return 0;
+ 
++err_disable_sysclk:
++      clk_disable_unprepare(csi2rx->sys_clk);
+ err_disable_pixclk:
+       for (; i > 0; i--) {
+               reset_control_assert(csi2rx->pixel_rst[i - 1]);
+@@ -213,6 +260,13 @@ static void csi2rx_stop(struct csi2rx_priv *csi2rx)
+ 
+       if (v4l2_subdev_call(csi2rx->source_subdev, video, s_stream, false))
+               dev_warn(csi2rx->dev, "Couldn't disable our subdev\n");
++
++      if (csi2rx->dphy) {
++              writel(0, csi2rx->base + CSI2RX_DPHY_LANE_CTRL_REG);
++
++              if (phy_power_off(csi2rx->dphy))
++                      dev_warn(csi2rx->dev, "Couldn't power off DPHY\n");
++      }
+ }
+ 
+ static int csi2rx_s_stream(struct v4l2_subdev *subdev, int enable)
+@@ -328,15 +382,6 @@ static int csi2rx_get_resources(struct csi2rx_priv *csi2rx,
+               return PTR_ERR(csi2rx->dphy);
+       }
+ 
+-      /*
+-       * FIXME: Once we'll have external D-PHY support, the check
+-       * will need to be removed.
+-       */
+-      if (csi2rx->dphy) {
+-              dev_err(&pdev->dev, "External D-PHY not supported yet\n");
+-              return -EINVAL;
+-      }
+-
+       ret = clk_prepare_enable(csi2rx->p_clk);
+       if (ret) {
+               dev_err(&pdev->dev, "Couldn't prepare and enable P clock\n");
+@@ -366,7 +411,7 @@ static int csi2rx_get_resources(struct csi2rx_priv *csi2rx,
+        * FIXME: Once we'll have internal D-PHY support, the check
+        * will need to be removed.
+        */
+-      if (csi2rx->has_internal_dphy) {
++      if (!csi2rx->dphy && csi2rx->has_internal_dphy) {
+               dev_err(&pdev->dev, "Internal D-PHY not supported yet\n");
+               return -EINVAL;
+       }
+@@ -492,6 +537,7 @@ static int csi2rx_probe(struct platform_device *pdev)
+       dev_info(&pdev->dev,
+                "Probed CSI2RX with %u/%u lanes, %u streams, %s D-PHY\n",
+                csi2rx->num_lanes, csi2rx->max_lanes, csi2rx->max_streams,
++               csi2rx->dphy ? "external" :
+                csi2rx->has_internal_dphy ? "internal" : "no");
+ 
+       return 0;
+-- 
+2.25.1
+