+++ /dev/null
-From e3d0d5fea3429218b79b58eb6cc96f5d5ab5dd31 Mon Sep 17 00:00:00 2001
-From: Zoltan HERPAI <wigyori@uid0.hu>
-Date: Mon, 29 May 2023 01:16:50 +0200
-Subject: [PATCH 97/97] riscv/6.1: jh7110: add watchdog node
-
-Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
----
- arch/riscv/boot/dts/starfive/jh7110.dtsi | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
-diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
-index 7ffeeded54a7..f3f563e3c5c2 100644
---- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
-+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
-@@ -582,6 +582,16 @@
- #gpio-cells = <2>;
- };
-
-+ watchdog@13070000 {
-+ compatible = "starfive,jh7110-wdt";
-+ reg = <0x0 0x13070000 0x0 0x10000>;
-+ clocks = <&syscrg JH7110_SYSCLK_WDT_APB>,
-+ <&syscrg JH7110_SYSCLK_WDT_CORE>;
-+ clock-names = "apb", "core";
-+ resets = <&syscrg JH7110_SYSRST_WDT_APB>,
-+ <&syscrg JH7110_SYSRST_WDT_CORE>;
-+ };
-+
- aoncrg: clock-controller@17000000 {
- compatible = "starfive,jh7110-aoncrg";
- reg = <0x0 0x17000000 0x0 0x10000>;
---
-2.20.1
-