jh71x0: update patches and config

[openwrt/staging/wigyori.git] / target / linux / jh71x0 / patches-6.1 / 0101-dt-bindings-phy-Add-StarFive-JH7110-PCIe-PHY.patch

diff --git a/target/linux/jh71x0/patches-6.1/0101-dt-bindings-phy-Add-StarFive-JH7110-PCIe-PHY.patch b/target/linux/jh71x0/patches-6.1/0101-dt-bindings-phy-Add-StarFive-JH7110-PCIe-PHY.patch
new file mode 100644 (file)
index 0000000..3122586
--- /dev/null
+++ b/target/linux/jh71x0/patches-6.1/0101-dt-bindings-phy-Add-StarFive-JH7110-PCIe-PHY.patch
@@ -0,0 +1,83 @@
+From bf04d2976521d69e5ee56d987ba8bebf95f7a909 Mon Sep 17 00:00:00 2001
+From: Minda Chen <minda.chen@starfivetech.com>
+Date: Thu, 18 May 2023 19:27:45 +0800
+Subject: [PATCH 101/129] dt-bindings: phy: Add StarFive JH7110 PCIe PHY
+
+Add StarFive JH7110 SoC PCIe 2.0 PHY dt-binding.
+PCIe PHY0 (phy@10210000) can be used as USB 3.0 PHY.
+
+Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
+Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+---
+ .../phy/starfive,jh7110-pcie-phy.yaml         | 58 +++++++++++++++++++
+ 1 file changed, 58 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
+
+diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
+new file mode 100644
+index 000000000..2e83a6164
+--- /dev/null
++++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
+@@ -0,0 +1,58 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/phy/starfive,jh7110-pcie-phy.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: StarFive JH7110 PCIe 2.0 PHY
++
++maintainers:
++  - Minda Chen <minda.chen@starfivetech.com>
++
++properties:
++  compatible:
++    const: starfive,jh7110-pcie-phy
++
++  reg:
++    maxItems: 1
++
++  "#phy-cells":
++    const: 0
++
++  starfive,sys-syscon:
++    $ref: /schemas/types.yaml#/definitions/phandle-array
++    items:
++      - items:
++          - description: phandle to System Register Controller sys_syscon node.
++          - description: PHY connect offset of SYS_SYSCONSAIF__SYSCFG register for USB PHY.
++    description:
++      The phandle to System Register Controller syscon node and the PHY connect offset
++      of SYS_SYSCONSAIF__SYSCFG register. Connect PHY to USB3 controller.
++
++  starfive,stg-syscon:
++    $ref: /schemas/types.yaml#/definitions/phandle-array
++    items:
++      - items:
++          - description: phandle to System Register Controller stg_syscon node.
++          - description: PHY mode offset of STG_SYSCONSAIF__SYSCFG register.
++          - description: PHY enable for USB offset of STG_SYSCONSAIF__SYSCFG register.
++    description:
++      The phandle to System Register Controller syscon node and the offset
++      of STG_SYSCONSAIF__SYSCFG register for PCIe PHY. Total 2 regsisters offset.
++
++required:
++  - compatible
++  - reg
++  - "#phy-cells"
++
++additionalProperties: false
++
++examples:
++  - |
++    phy@10210000 {
++        compatible = "starfive,jh7110-pcie-phy";
++        reg = <0x10210000 0x10000>;
++        #phy-cells = <0>;
++        starfive,sys-syscon = <&sys_syscon 0x18>;
++        starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>;
++    };
+-- 
+2.25.1
+