jh71x0: add new target for StarFive JH7100/7110 SoC

[openwrt/staging/wigyori.git] / target / linux / jh71x0 / patches-6.1 / 0114-RISC-V-Add-StarFive-JH7100-audio-clock-node.patch

diff --git a/target/linux/jh71x0/patches-6.1/0114-RISC-V-Add-StarFive-JH7100-audio-clock-node.patch b/target/linux/jh71x0/patches-6.1/0114-RISC-V-Add-StarFive-JH7100-audio-clock-node.patch
new file mode 100644 (file)
index 0000000..92b94d8
--- /dev/null
+++ b/target/linux/jh71x0/patches-6.1/0114-RISC-V-Add-StarFive-JH7100-audio-clock-node.patch
@@ -0,0 +1,37 @@
+From 908d47cb1cb38bb92f95284ed800b1a059cef641 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Sat, 20 Nov 2021 17:13:22 +0100
+Subject: [PATCH 114/121] RISC-V: Add StarFive JH7100 audio clock node
+
+Add device tree node for the audio clocks on the StarFive JH7100 RISC-V
+SoC.
+
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ arch/riscv/boot/dts/starfive/jh7100.dtsi | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
+index b3f944c1b5b9..930721e87ae8 100644
+--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
++++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
+@@ -133,6 +133,16 @@
+                       riscv,ndev = <133>;
+               };
+ 
++              audclk: clock-controller@10480000 {
++                      compatible = "starfive,jh7100-audclk";
++                      reg = <0x0 0x10480000 0x0 0x10000>;
++                      clocks = <&clkgen JH7100_CLK_AUDIO_SRC>,
++                               <&clkgen JH7100_CLK_AUDIO_12288>,
++                               <&clkgen JH7100_CLK_DOM7AHB_BUS>;
++                      clock-names = "audio_src", "audio_12288", "dom7ahb_bus";
++                      #clock-cells = <1>;
++              };
++
+               clkgen: clock-controller@11800000 {
+                       compatible = "starfive,jh7100-clkgen";
+                       reg = <0x0 0x11800000 0x0 0x10000>;
+-- 
+2.20.1
+