lantiq: Use the BAR0 base address in the ath PCI fixup code

[openwrt/openwrt.git] / target / linux / lantiq / patches-3.18 / 0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch

diff --git a/target/linux/lantiq/patches-3.18/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch b/target/linux/lantiq/patches-3.18/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch
index 094d16c5c9d210856c5155fd901d01641123a64a..ec769ccf63c3699d08deadf9e6ae1bc68a6e3f12 100644 (file)
--- a/target/linux/lantiq/patches-3.18/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch
+++ b/target/linux/lantiq/patches-3.18/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch
@@ -431,8 +431,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +#include <linux/delay.h>
 +#include <lantiq_soc.h>
 +
-+#define LTQ_PCI_MEM_BASE              0x18000000
-+
 +struct ath_fixup {
 +      u16             *cal_data;
 +      unsigned        slot;
@@ -448,6 +446,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +      u16 cmd;
 +      u32 bar0;
 +      u32 val;
++      u32 base;
 +      unsigned i;
 +
 +      for (i = 0; i < ath_num_fixups; i++) {
@@ -471,14 +470,15 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +
 +      pr_info("pci %s: fixup device configuration\n", pci_name(dev));
 +
-+      mem = ioremap(LTQ_PCI_MEM_BASE, 0x10000);
++      base = dev->resource[0].start;
++      mem = ioremap(base, 0x10000);
 +      if (!mem) {
 +              pr_err("pci %s: ioremap error\n", pci_name(dev));
 +              return;
 +      }
 +
 +      pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0);
-+      pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, LTQ_PCI_MEM_BASE);
++      pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, base);
 +      pci_read_config_word(dev, PCI_COMMAND, &cmd);
 +      cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 +      pci_write_config_word(dev, PCI_COMMAND, cmd);