layerscape: add 64b/32b target for ls1012ardb device

[openwrt/staging/yousong.git] / target / linux / layerscape / patches-4.4 / 1108-mtd-fsl-quadspi-add-multi-flash-chip-R-W-on-ls2080a.patch

diff --git a/target/linux/layerscape/patches-4.4/1108-mtd-fsl-quadspi-add-multi-flash-chip-R-W-on-ls2080a.patch b/target/linux/layerscape/patches-4.4/1108-mtd-fsl-quadspi-add-multi-flash-chip-R-W-on-ls2080a.patch
new file mode 100644 (file)
index 0000000..4a7a5cb
--- /dev/null
+++ b/target/linux/layerscape/patches-4.4/1108-mtd-fsl-quadspi-add-multi-flash-chip-R-W-on-ls2080a.patch
@@ -0,0 +1,42 @@
+From d3a8ee41170ff9e5298ff354c77ff99439dfe2bf Mon Sep 17 00:00:00 2001
+From: Yunhui Cui <yunhui.cui@nxp.com>
+Date: Thu, 10 Mar 2016 11:33:40 +0800
+Subject: [PATCH 108/113] mtd: fsl-quadspi: add multi flash chip R/W on
+ ls2080a
+
+There is a hardware feature that qspi_amba_base is added
+internally by SOC design on ls2080a. so memmap_phy need not
+be added in driver. If memmap_phy is added, the flash A1
+addr space is [0, memmap_phy] which far more than flash size.
+The AMBA memory will be divided into four parts and assign to
+every chipselect. Every channel will has two valid chipselects.
+
+Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
+---
+ drivers/mtd/spi-nor/fsl-quadspi.c |   14 ++++++++++----
+ 1 file changed, 10 insertions(+), 4 deletions(-)
+
+--- a/drivers/mtd/spi-nor/fsl-quadspi.c
++++ b/drivers/mtd/spi-nor/fsl-quadspi.c
+@@ -744,11 +744,17 @@ static void fsl_qspi_set_map_addr(struct
+ {
+       int nor_size = q->nor_size;
+       void __iomem *base = q->iobase;
++      u32 mem_base;
+ 
+-      qspi_writel(q, nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
+-      qspi_writel(q, nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
+-      qspi_writel(q, nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
+-      qspi_writel(q, nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
++      if (has_added_amba_base_internal(q))
++              mem_base = 0x0;
++      else
++              mem_base = q->memmap_phy;
++
++      qspi_writel(q, nor_size + mem_base, base + QUADSPI_SFA1AD);
++      qspi_writel(q, nor_size * 2 + mem_base, base + QUADSPI_SFA2AD);
++      qspi_writel(q, nor_size * 3 + mem_base, base + QUADSPI_SFB1AD);
++      qspi_writel(q, nor_size * 4 + mem_base, base + QUADSPI_SFB2AD);
+ }
+ 
+ /*