layerscape: add 64b/32b target for ls1012ardb device

[openwrt/openwrt.git] / target / linux / layerscape / patches-4.4 / 8073-ls1012a-added-clock-configuration.patch

diff --git a/target/linux/layerscape/patches-4.4/8073-ls1012a-added-clock-configuration.patch b/target/linux/layerscape/patches-4.4/8073-ls1012a-added-clock-configuration.patch
new file mode 100644 (file)
index 0000000..3936c80
--- /dev/null
+++ b/target/linux/layerscape/patches-4.4/8073-ls1012a-added-clock-configuration.patch
@@ -0,0 +1,61 @@
+From 9112596c3c7b7b8b1eded3323765fa711dc58e74 Mon Sep 17 00:00:00 2001
+From: Tang Yuantian <Yuantian.Tang@nxp.com>
+Date: Thu, 25 Aug 2016 10:38:28 +0800
+Subject: [PATCH 073/113] ls1012a: added clock configuration
+
+commit c9c11181191938b77bfd61e5094a63955cf711fd
+[context adjustment]
+[don't apply fsl-ls1012a.dtsi]
+
+Currently ls1012a used the clock configuration of ls1043a's.
+But there is a little different between them. This patch added
+ls1012a its own clock configuration.
+
+Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
+Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
+---
+ drivers/clk/clk-qoriq.c |   19 +++++++++++++++++++
+ 1 file changed, 19 insertions(+)
+
+--- a/drivers/clk/clk-qoriq.c
++++ b/drivers/clk/clk-qoriq.c
+@@ -195,6 +195,14 @@ static const struct clockgen_muxinfo t10
+       }
+ };
+ 
++static const struct clockgen_muxinfo ls1012a_cmux = {
++      {
++              [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
++              {},
++              [2] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
++      }
++};
++
+ static const struct clockgen_muxinfo t1040_cmux = {
+       {
+               [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
+@@ -475,6 +483,16 @@ static const struct clockgen_chipinfo ch
+               .pll_mask = 0x03,
+       },
+       {
++              .compat = "fsl,ls1012a-clockgen",
++              .cmux_groups = {
++                      &ls1012a_cmux
++              },
++              .cmux_to_group = {
++                      0, -1
++              },
++              .pll_mask = 0x03,
++      },
++      {
+               .compat = "fsl,ls1043a-clockgen",
+               .init_periph = t2080_init_periph,
+               .cmux_groups = {
+@@ -1268,6 +1286,7 @@ CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qo
+ CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
+ CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
+ CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
++CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init);
+ 
+ /* Legacy nodes */
+ CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);