/* FLEXCAN memory error control register (MECR) bits */
#define FLEXCAN_MECR_ECRWRDIS BIT(31)
-@@ -1323,6 +1324,7 @@ static int flexcan_chip_start(struct net
+@@ -1322,6 +1323,7 @@ static int flexcan_chip_start(struct net
reg_fdctrl = priv->read(®s->fdctrl) & ~FLEXCAN_FDCTRL_FDRATE;
reg_fdctrl &= ~(FLEXCAN_FDCTRL_MBDSR1(0x3) | FLEXCAN_FDCTRL_MBDSR0(0x3));
reg_mcr = priv->read(®s->mcr) & ~FLEXCAN_MCR_FDEN;
/* support BRS when set CAN FD mode
* 64 bytes payload per MB and 7 MBs per RAM block by default
-@@ -1332,10 +1334,14 @@ static int flexcan_chip_start(struct net
+@@ -1331,10 +1333,14 @@ static int flexcan_chip_start(struct net
reg_fdctrl |= FLEXCAN_FDCTRL_FDRATE;
reg_fdctrl |= FLEXCAN_FDCTRL_MBDSR1(0x3) | FLEXCAN_FDCTRL_MBDSR0(0x3);
reg_mcr |= FLEXCAN_MCR_FDEN;
}
if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
-@@ -1853,7 +1859,7 @@ static int flexcan_probe(struct platform
+@@ -1852,7 +1858,7 @@ static int flexcan_probe(struct platform
if (priv->devtype_data->quirks & FLEXCAN_QUIRK_TIMESTAMP_SUPPORT_FD) {
if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {