leon: add SDK patches from buildroot-2022.02-1.2/5.10.175

[openwrt/staging/wigyori.git] / target / linux / leon / patches-5.15 / 0010-sparc32-leon-Handle-self-clearing-FSR.ftt-when-savin.patch

diff --git a/target/linux/leon/patches-5.15/0010-sparc32-leon-Handle-self-clearing-FSR.ftt-when-savin.patch b/target/linux/leon/patches-5.15/0010-sparc32-leon-Handle-self-clearing-FSR.ftt-when-savin.patch
new file mode 100644 (file)
index 0000000..13f94cd
--- /dev/null
+++ b/target/linux/leon/patches-5.15/0010-sparc32-leon-Handle-self-clearing-FSR.ftt-when-savin.patch
@@ -0,0 +1,51 @@
+From ce71c62289d17a6e7d809759f6b10297bb066d11 Mon Sep 17 00:00:00 2001
+From: Andreas Larsson <andreas@gaisler.com>
+Date: Wed, 20 Sep 2017 09:10:46 +0200
+Subject: [PATCH 10/32] sparc32,leon: Handle self clearing FSR.ftt when saving
+ FPU registers
+
+GRFPU self clears the ftt field after a STFSR. Make sure that the ftt
+field is not for cases with multiple STFSRs.
+
+Signed-off-by: Andreas Larsson <andreas@gaisler.com>
+---
+ arch/sparc/kernel/entry.S | 8 +++++++-
+ 1 file changed, 7 insertions(+), 1 deletion(-)
+
+diff --git a/arch/sparc/kernel/entry.S b/arch/sparc/kernel/entry.S
+index b56f489e38bb..87c68aeeb794 100644
+--- a/arch/sparc/kernel/entry.S
++++ b/arch/sparc/kernel/entry.S
+@@ -1062,6 +1062,7 @@ fpsave:
+       st      %fsr, [%o1]     ! this can trap on us if fpu is in bogon state
+       ld      [%o1], %g1
+       set     0x2000, %g4
++      set     0x1c000, %g5
+       andcc   %g1, %g4, %g0
+       be      2f
+        mov    0, %g2
+@@ -1072,6 +1073,10 @@ fpsave:
+ fpsave_magic:
+       st      %fsr, [%o1]
+       ld      [%o1], %g3
++      andn    %g3, %g5, %g3 /* ftt gets cleared on stfsr for GRFPU... */
++      and     %g1, %g5, %g1
++      or      %g1, %g3, %g3
++      st      %g3, [%o1]    /* ... so set ftt field from first fsr read */
+       andcc   %g3, %g4, %g0
+       add     %g2, 1, %g2
+       bne     1b
+@@ -1108,8 +1113,9 @@ fpsave_catch:
+        st     %fsr, [%o1]
+ 
+ fpsave_catch2:
++      st      %fsr, [%o1] /* In this case, this is the first successful fsr read */
+       b       fpsave + 4
+-       st     %fsr, [%o1]
++       ld     [%o1], %g1 /* so take care of it for GRFPU ftt field handling */
+ 
+       /* void fpload(unsigned long *fpregs, unsigned long *fsr); */
+ 
+-- 
+2.34.1
+