mediatek: backport upstream mediatek patches

[openwrt/staging/blogic.git] / target / linux / mediatek / patches-4.14 / 0175-net-mediatek-remove-superfluous-pin-setup-for-MT7622.patch

diff --git a/target/linux/mediatek/patches-4.14/0175-net-mediatek-remove-superfluous-pin-setup-for-MT7622.patch b/target/linux/mediatek/patches-4.14/0175-net-mediatek-remove-superfluous-pin-setup-for-MT7622.patch
new file mode 100644 (file)
index 0000000..3116f03
--- /dev/null
+++ b/target/linux/mediatek/patches-4.14/0175-net-mediatek-remove-superfluous-pin-setup-for-MT7622.patch
@@ -0,0 +1,106 @@
+From d96cf7e724105dc73f623c2019ab5bc78cef036e Mon Sep 17 00:00:00 2001
+From: Sean Wang <sean.wang@mediatek.com>
+Date: Wed, 20 Dec 2017 17:47:06 +0800
+Subject: [PATCH 175/224] net: mediatek: remove superfluous pin setup for
+ MT7622 SoC
+
+Remove superfluous pin setup to get out of accessing invalid I/O pin
+registers because the way for pin configuring tends to be different from
+various SoCs and thus it should be better being managed and controlled by
+the pinctrl driver which MT7622 already can support.
+
+Signed-off-by: Sean Wang <sean.wang@mediatek.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 35 +++++++++++++++++------------
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h |  3 +++
+ 2 files changed, 24 insertions(+), 14 deletions(-)
+
+Index: linux-4.14.37/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+===================================================================
+--- linux-4.14.37.orig/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ linux-4.14.37/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -1976,14 +1976,16 @@ static int mtk_hw_init(struct mtk_eth *e
+       }
+       regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
+ 
+-      /* Set GE2 driving and slew rate */
+-      regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
++      if (eth->pctl) {
++              /* Set GE2 driving and slew rate */
++              regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
+ 
+-      /* set GE2 TDSEL */
+-      regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
++              /* set GE2 TDSEL */
++              regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
+ 
+-      /* set GE2 TUNE */
+-      regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
++              /* set GE2 TUNE */
++              regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
++      }
+ 
+       /* Set linkdown as the default for each GMAC. Its own MCR would be set
+        * up with the more appropriate value when mtk_phy_link_adjust call is
+@@ -2568,11 +2570,13 @@ static int mtk_probe(struct platform_dev
+               }
+       }
+ 
+-      eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+-                                                  "mediatek,pctl");
+-      if (IS_ERR(eth->pctl)) {
+-              dev_err(&pdev->dev, "no pctl regmap found\n");
+-              return PTR_ERR(eth->pctl);
++      if (eth->soc->required_pctl) {
++              eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
++                                                          "mediatek,pctl");
++              if (IS_ERR(eth->pctl)) {
++                      dev_err(&pdev->dev, "no pctl regmap found\n");
++                      return PTR_ERR(eth->pctl);
++              }
+       }
+ 
+       for (i = 0; i < 3; i++) {
+@@ -2698,17 +2702,20 @@ static int mtk_remove(struct platform_de
+ 
+ static const struct mtk_soc_data mt2701_data = {
+       .caps = MTK_GMAC1_TRGMII,
+-      .required_clks = MT7623_CLKS_BITMAP
++      .required_clks = MT7623_CLKS_BITMAP,
++      .required_pctl = true,
+ };
+ 
+ static const struct mtk_soc_data mt7622_data = {
+       .caps = MTK_DUAL_GMAC_SHARED_SGMII | MTK_GMAC1_ESW,
+-      .required_clks = MT7622_CLKS_BITMAP
++      .required_clks = MT7622_CLKS_BITMAP,
++      .required_pctl = false,
+ };
+ 
+ static const struct mtk_soc_data mt7623_data = {
+       .caps = MTK_GMAC1_TRGMII,
+-      .required_clks = MT7623_CLKS_BITMAP
++      .required_clks = MT7623_CLKS_BITMAP,
++      .required_pctl = true,
+ };
+ 
+ const struct of_device_id of_mtk_match[] = {
+Index: linux-4.14.37/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+===================================================================
+--- linux-4.14.37.orig/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ linux-4.14.37/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -574,10 +574,13 @@ struct mtk_rx_ring {
+  * @caps                      Flags shown the extra capability for the SoC
+  * @required_clks             Flags shown the bitmap for required clocks on
+  *                            the target SoC
++ * @required_pctl             A bool value to show whether the SoC requires
++ *                            the extra setup for those pins used by GMAC.
+  */
+ struct mtk_soc_data {
+       u32             caps;
+       u32             required_clks;
++      bool            required_pctl;
+ };
+ 
+ /* currently no SoC has more than 2 macs */