mediatek: replace hack for MaxLinear 2.5G PHY

[openwrt/staging/jogo.git] / target / linux / mediatek / patches-5.15 / 732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch

diff --git a/target/linux/mediatek/patches-5.15/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch b/target/linux/mediatek/patches-5.15/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch
new file mode 100644 (file)
index 0000000..598d9d0
--- /dev/null
+++ b/target/linux/mediatek/patches-5.15/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch
@@ -0,0 +1,63 @@
+From a969b663c866129ed9eb217785a6574fbe826f1d Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 6 Apr 2023 23:36:50 +0100
+Subject: [PATCH] net: phy: mxl-gpy: don't use SGMII AN if using phylink
+
+MAC drivers using phylink expect SGMII in-band-status to be switched off
+when attached to a PHY. Make sure this is the case also for mxl-gpy which
+keeps SGMII in-band-status in case of SGMII interface mode is used.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/net/phy/mxl-gpy.c | 19 ++++++++++++++++---
+ 1 file changed, 16 insertions(+), 3 deletions(-)
+
+--- a/drivers/net/phy/mxl-gpy.c
++++ b/drivers/net/phy/mxl-gpy.c
+@@ -191,8 +191,11 @@ static bool gpy_2500basex_chk(struct phy
+ 
+       phydev->speed = SPEED_2500;
+       phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
+-      phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
+-                     VSPEC1_SGMII_CTRL_ANEN, 0);
++
++      if (!phydev->phylink)
++              phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
++                             VSPEC1_SGMII_CTRL_ANEN, 0);
++
+       return true;
+ }
+ 
+@@ -216,6 +219,14 @@ static int gpy_config_aneg(struct phy_de
+       u32 adv;
+       int ret;
+ 
++      /* Disable SGMII auto-negotiation if using phylink */
++      if (phydev->phylink) {
++              ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
++                                   VSPEC1_SGMII_CTRL_ANEN, 0);
++              if (ret < 0)
++                      return ret;
++      }
++
+       if (phydev->autoneg == AUTONEG_DISABLE) {
+               /* Configure half duplex with genphy_setup_forced,
+                * because genphy_c45_pma_setup_forced does not support.
+@@ -306,6 +317,8 @@ static void gpy_update_interface(struct
+       switch (phydev->speed) {
+       case SPEED_2500:
+               phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
++              if (phydev->phylink)
++                      break;
+               ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
+                                    VSPEC1_SGMII_CTRL_ANEN, 0);
+               if (ret < 0)
+@@ -317,7 +330,7 @@ static void gpy_update_interface(struct
+       case SPEED_100:
+       case SPEED_10:
+               phydev->interface = PHY_INTERFACE_MODE_SGMII;
+-              if (gpy_sgmii_aneg_en(phydev))
++              if (phydev->phylink || gpy_sgmii_aneg_en(phydev))
+                       break;
+               /* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed
+                * if ANEG is disabled (in 2500-BaseX mode).