ramips: add Xiaomi Mi Router 3G support

[openwrt/staging/lynxis.git] / target / linux / ramips / dts / MIR3G.dts

diff --git a/target/linux/ramips/dts/MIR3G.dts b/target/linux/ramips/dts/MIR3G.dts
new file mode 100644 (file)
index 0000000..0cdb6d5
--- /dev/null
+++ b/target/linux/ramips/dts/MIR3G.dts
@@ -0,0 +1,163 @@
+/dts-v1/;
+
+#include "mt7621.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+       compatible = "xiaomi,mir3g", "mediatek,mt7621-soc";
+       model = "Xiaomi Mi Router 3G";
+
+       memory@0 {
+               device_type = "memory";
+               reg = <0x0 0x10000000>;
+       };
+
+       chosen {
+               bootargs = "console=ttyS0,115200n8";
+       };
+
+       gpio-leds {
+               compatible = "gpio-leds";
+
+               wan {
+                       label = "mir3g:red:wan";
+                       gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+               };
+
+               usb {
+                       label = "mir3g:blue:usb";
+                       gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
+               };
+
+               status {
+                       label = "mir3g:yellow:status";
+                       gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
+               };
+       };
+
+       gpio-keys-polled {
+               compatible = "gpio-keys-polled";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               poll-interval = <20>;
+
+               reset {
+                       label = "reset";
+                       gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
+                       linux,code = <KEY_RESTART>;
+               };
+       };
+};
+
+&nand {
+       status = "okay";
+
+       partition@0 {
+               label = "Bootloader";
+               reg = <0x0 0x80000>;
+               read-only;
+       };
+
+       partition@80000 {
+               label = "Config";
+               reg = <0x80000 0x40000>;
+               read-only;
+       };
+
+       partition@c0000 {
+               label = "Bdata";
+               reg = <0xc0000 0x40000>;
+               read-only;
+       };
+
+       factory: partition@100000 {
+               label = "Factory";
+               reg = <0x100000 0x40000>;
+               read-only;
+       };
+
+       partition@140000 {
+               label = "crash";
+               reg = <0x140000 0x40000>;
+               read-only;
+       };
+
+       partition@180000 {
+               label = "crash_syslog";
+               reg = <0x180000 0x40000>;
+               read-only;
+       };
+
+       partition@1c0000 {
+               label = "reserved0";
+               reg = <0x1c0000 0x40000>;
+               read-only;
+       };
+
+       /* 
+        * kernel0 partition should be erased, so 
+        * u-boot in failsafe routine switches 
+        * to next one looking for kernel image.
+        * To remind about this fact rename kernel0
+        * into kernel_erase.
+        */
+       partition@200000 {
+               label = "kernel_erase";
+               reg = <0x200000 0x400000>;
+       };
+
+       partition@600000 {
+               label = "kernel";
+               reg = <0x600000 0x400000>;
+       };
+
+       /* ubi partition is the result of squashing
+        * next consequent stock partitions:
+        * - rootfs0 (rootfs partition for stock kernel0), 
+        * - rootfs1 (rootfs partition for stock failsafe kernel1), 
+        * - overlay (used as ubi overlay in stock fw)
+        * resulting 117,5MiB space for packages.
+        */
+       partition@a00000 {
+               label = "ubi";
+               reg = <0xa00000 0x7580000>;
+       };
+};
+
+&pcie {
+       status = "okay";
+
+       pcie0 {
+               wifi@14c3,7603 {
+                       compatible = "pci14c3,7603";
+                       reg = <0x0000 0 0 0 0>;
+                       mediatek,mtd-eeprom = <&factory 0x0000>;
+                       ieee80211-freq-limit = <2400000 2500000>;
+               };
+       };      
+
+       pcie1 {
+               wifi@14c3,7662 {
+                       compatible = "pci14c3,7662";
+                       reg = <0x0000 0 0 0 0>;
+                       mediatek,mtd-eeprom = <&factory 0x8000>;
+                       ieee80211-freq-limit = <5000000 6000000>;
+               };
+       };
+};
+
+&ethernet {
+       mtd-mac-address = <&factory 0xe000>;
+       mediatek,portmap = "lwlll";
+};
+
+&pinctrl {
+       state_default: pinctrl0 {
+               gpio {
+                       ralink,group = "jtag", "uart3", "wdt";
+                       ralink,function = "gpio";
+               };
+       };
+};