ramips: fix firmware splitter for edimax based boards
[openwrt/staging/wigyori.git] / target / linux / ramips / dts / PSG1208.dts
index 547da2fdfa7353d4e4874aa343a57e0be2a62ff7..de8d11abeebdfab72c7af077cf7adb493c33debc 100644 (file)
@@ -2,35 +2,41 @@
 
 #include "mt7620a.dtsi"
 
+#include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 
 / {
-       compatible = "PSG1208", "ralink,mt7620a-soc";
+       compatible = "phicomm,psg1208", "ralink,mt7620a-soc";
        model = "Phicomm PSG1208";
 
+       aliases {
+               led-boot = &led_wps;
+               led-failsafe = &led_wps;
+               led-running = &led_wps;
+               led-upgrade = &led_wps;
+       };
+
        gpio-leds {
                compatible = "gpio-leds";
 
-               wan {
+               led_wps: wps {
                        label = "psg1208:white:wps";
-                       gpios = <&gpio1 15 1>;
+                       gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
                };
 
                wlan {
                        label = "psg1208:white:wlan2g";
-                       gpios = <&gpio3 0 1>;
+                       gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
                };
        };
 
        gpio-keys-polled {
                compatible = "gpio-keys-polled";
-               #address-cells = <1>;
-               #size-cells = <0>;
                poll-interval = <20>;
 
                reset {
                        label = "reset";
-                       gpios = <&gpio0 1 1>;
+                       gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
                        linux,code = <KEY_RESTART>;
                };
        };
        status = "okay";
 
        m25p80@0 {
-               #address-cells = <1>;
-               #size-cells = <1>;
                compatible = "jedec,spi-nor";
                reg = <0>;
                spi-max-frequency = <10000000>;
 
-               partition@0 {
-                       label = "u-boot";
-                       reg = <0x0 0x30000>;
-                       read-only;
-               };
-
-               partition@20000 {
-                       label = "u-boot-env";
-                       reg = <0x30000 0x10000>;
-                       read-only;
-               };
-
-               factory: partition@30000 {
-                       label = "factory";
-                       reg = <0x40000 0x10000>;
-                       read-only;
-               };
-
-               partition@40000 {
-                       label = "firmware";
-                       reg = <0x50000 0x7b0000>;
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       partition@0 {
+                               label = "u-boot";
+                               reg = <0x0 0x30000>;
+                               read-only;
+                       };
+
+                       partition@20000 {
+                               label = "u-boot-env";
+                               reg = <0x30000 0x10000>;
+                               read-only;
+                       };
+
+                       factory: partition@30000 {
+                               label = "factory";
+                               reg = <0x40000 0x10000>;
+                               read-only;
+                       };
+
+                       partition@40000 {
+                               compatible = "denx,uimage";
+                               label = "firmware";
+                               reg = <0x50000 0x7b0000>;
+                       };
                };
        };
 };
@@ -82,7 +93,7 @@
 &pinctrl {
        state_default: pinctrl0 {
                gpio {
-                       ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "ephy", "wled", "nd_sd";
+                       ralink,group = "i2c", "spi refclk", "wled";
                        ralink,function = "gpio";
                };
        };
 
 &pcie {
        status = "okay";
+};
 
-       pcie-bridge {
-               mt76@0,0 {
-                       reg = <0x0000 0 0 0 0>;
-                       device_type = "pci";
-                       mediatek,mtd-eeprom = <&factory 0x8000>;
-                       ieee80211-freq-limit = <5000000 6000000>;
-               };
+&pcie0 {
+       mt76@0,0 {
+               reg = <0x0000 0 0 0 0>;
+               mediatek,mtd-eeprom = <&factory 0x8000>;
+               ieee80211-freq-limit = <5000000 6000000>;
        };
 };