#include "mt7621.dtsi"
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
+ compatible = "storylink,sap-g3200u3", "mediatek,mt7621-soc";
model = "STORYLiNK SAP-G3200U3";
memory@0 {
bootargs = "console=ttyS0,57600";
};
- gpio-leds {
+ leds {
compatible = "gpio-leds";
usb {
label = "sap-g3200u3:green:usb";
- gpios = <&gpio0 13 1>;
+ gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
+ trigger-sources = <&xhci_ehci_port1>, <&ehci_port2>;
+ linux,default-trigger = "usbport";
};
};
- gpio-keys-polled {
+ keys {
compatible = "gpio-keys-polled";
- #address-cells = <1>;
- #size-cells = <0>;
poll-interval = <20>;
reset {
label = "reset";
- gpios = <&gpio0 16 1>;
+ gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
rfkill {
label = "rfkill";
- gpios = <&gpio0 14 1>;
+ gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RFKILL>;
};
};
status = "okay";
m25p80@0 {
- #address-cells = <1>;
- #size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
- m25p,chunked-io = <32>;
- partition@0 {
- label = "u-boot";
- reg = <0x0 0x30000>;
- read-only;
- };
-
- partition@30000 {
- label = "u-boot-env";
- reg = <0x30000 0x1000>;
- read-only;
- };
-
- partition@31000 {
- label = "config";
- reg = <0x31000 0xf000>;
- read-only;
- };
-
- factory: partition@40000 {
- label = "factory";
- reg = <0x40000 0x10000>;
- read-only;
- };
-
- partition@50000 {
- label = "firmware";
- reg = <0x50000 0x7b0000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x30000>;
+ read-only;
+ };
+
+ partition@30000 {
+ label = "u-boot-env";
+ reg = <0x30000 0x1000>;
+ read-only;
+ };
+
+ partition@31000 {
+ label = "config";
+ reg = <0x31000 0xf000>;
+ read-only;
+ };
+
+ factory: partition@40000 {
+ label = "factory";
+ reg = <0x40000 0x10000>;
+ read-only;
+ };
+
+ partition@50000 {
+ compatible = "denx,uimage";
+ label = "firmware";
+ reg = <0x50000 0x7b0000>;
+ };
};
};
};
&pcie {
status = "okay";
+};
- pcie0 {
- mt76@0,0 {
- reg = <0x0000 0 0 0 0>;
- device_type = "pci";
- mediatek,mtd-eeprom = <&factory 0x8000>;
- ieee80211-freq-limit = <5000000 6000000>;
- };
+&pcie0 {
+ mt76@0,0 {
+ reg = <0x0000 0 0 0 0>;
+ mediatek,mtd-eeprom = <&factory 0x8000>;
+ ieee80211-freq-limit = <5000000 6000000>;
};
+};
- pcie1 {
- mt76@1,0 {
- reg = <0x0000 0 0 0 0>;
- device_type = "pci";
- mediatek,mtd-eeprom = <&factory 0x0000>;
- ieee80211-freq-limit = <2400000 2500000>;
- };
+&pcie1 {
+ mt76@0,0 {
+ reg = <0x0000 0 0 0 0>;
+ mediatek,mtd-eeprom = <&factory 0x0000>;
+ ieee80211-freq-limit = <2400000 2500000>;
};
};