// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/dts-v1/;
#include "mt7620a.dtsi"
compatible = "gpio-leds";
rssi {
- label = "hdrm200:red:rssi";
+ label = "red:rssi";
gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
};
led_system: system {
- label = "hdrm200:green:system";
+ label = "green:system";
gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
};
air {
- label = "hdrm200:green:wifi";
+ label = "green:wifi";
gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
};
};
read-only;
};
- factory: partition@40000 {
+ partition@40000 {
label = "factory";
reg = <0x40000 0x10000>;
read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ eeprom_factory_0: eeprom@0 {
+ reg = <0x0 0x200>;
+ };
+
+ eeprom_factory_8000: eeprom@8000 {
+ reg = <0x8000 0x200>;
+ };
+
+ macaddr_factory_4: macaddr@4 {
+ reg = <0x4 0x6>;
+ };
+ };
};
- firmware: partition@50000 {
+ partition@50000 {
compatible = "denx,uimage";
label = "firmware";
reg = <0x50000 0xfb0000>;
};
};
-&gpio0 {
- status = "okay";
-};
-
&gpio1 {
status = "okay";
};
};
ðernet {
- status = "okay";
-
- mtd-mac-address = <&factory 0x4>;
pinctrl-names = "default";
pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
+ nvmem-cells = <&macaddr_factory_4>;
+ nvmem-cell-names = "mac-address";
+
port@4 {
status = "okay";
phy-handle = <&phy4>;
};
};
+&gsw {
+ mediatek,port4-gmac;
+ mediatek,ephy-base = /bits/ 8 <8>;
+};
+
&wmac {
- ralink,mtd-eeprom = <&factory 0>;
+ nvmem-cells = <&eeprom_factory_0>;
+ nvmem-cell-names = "eeprom";
};
&state_default {
default {
- ralink,group = "i2c", "uartf", "pa", "spi refclk",
+ groups = "i2c", "uartf", "pa", "spi refclk",
"wled";
- ralink,function = "gpio";
+ function = "gpio";
};
};
wifi@0,0 {
compatible = "mediatek,mt76";
reg = <0x0000 0 0 0 0>;
- mediatek,mtd-eeprom = <&factory 0x8000>;
+ nvmem-cells = <&eeprom_factory_8000>;
+ nvmem-cell-names = "eeprom";
ieee80211-freq-limit = <5000000 6000000>;
};
};