ramips/mt7620: Name DTS files based on scheme

[openwrt/openwrt.git] / target / linux / ramips / dts / mt7620a_planex_cs-qr10.dts

diff --git a/target/linux/ramips/dts/mt7620a_planex_cs-qr10.dts b/target/linux/ramips/dts/mt7620a_planex_cs-qr10.dts
new file mode 100644 (file)
index 0000000..dadd37a
--- /dev/null
+++ b/target/linux/ramips/dts/mt7620a_planex_cs-qr10.dts
@@ -0,0 +1,158 @@
+/dts-v1/;
+
+#include "mt7620a.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+       compatible = "planex,cs-qr10", "ralink,mt7620a-soc";
+       model = "Planex CS-QR10";
+
+       aliases {
+               led-boot = &led_power;
+               led-failsafe = &led_power;
+               led-running = &led_power;
+               led-upgrade = &led_power;
+       };
+
+       leds {
+               compatible = "gpio-leds";
+
+               led_power: power {
+                       label = "cs-qr10:red:power";
+                       gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+               };
+       };
+
+       keys {
+               compatible = "gpio-keys-polled";
+               poll-interval = <20>;
+
+               s1 {
+                       label = "reset";
+                       gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_RESTART>;
+               };
+
+               s2 {
+                       label = "wps";
+                       gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_WPS_BUTTON>;
+               };
+       };
+};
+
+&gpio0 {
+       status = "okay";
+};
+
+&gpio1 {
+       status = "okay";
+};
+
+&gpio2 {
+       status = "okay";
+};
+
+&gpio3 {
+       status = "okay";
+};
+
+&i2c {
+       status = "okay";
+};
+
+&i2s {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcm_i2s_pins>;
+};
+
+&spi0 {
+       status = "okay";
+
+       m25p80@0 {
+               compatible = "jedec,spi-nor";
+               reg = <0>;
+               spi-max-frequency = <10000000>;
+
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       partition@0 {
+                               label = "u-boot";
+                               reg = <0x0 0x30000>;
+                               read-only;
+                       };
+
+                       partition@30000 {
+                               label = "u-boot-env";
+                               reg = <0x30000 0x10000>;
+                               read-only;
+                       };
+
+                       factory: partition@40000 {
+                               label = "factory";
+                               reg = <0x40000 0x10000>;
+                               read-only;
+                       };
+
+                       partition@50000 {
+                               compatible = "denx,uimage";
+                               label = "firmware";
+                               reg = <0x50000 0x7b0000>;
+                       };
+               };
+       };
+};
+
+&pcm {
+       status = "okay";
+};
+
+&gdma {
+       status = "okay";
+};
+
+&pinctrl {
+       state_default: pinctrl0 {
+               gpio {
+                       ralink,group = "spi refclk", "rgmii1";
+                       ralink,function = "gpio";
+               };
+               wdt {
+                       ralink,group = "wdt";
+                       ralink,function = "wdt refclk";
+               };
+       };
+};
+
+&ethernet {
+       pinctrl-names = "default";
+       pinctrl-0 = <&ephy_pins>;
+       mtd-mac-address = <&factory 0x4>;
+       mediatek,portmap = "llllw";
+};
+
+&gsw {
+       ralink,port4 = "ephy";
+};
+
+&sdhci {
+       status = "okay";
+};
+
+&ehci {
+       status = "okay";
+};
+
+&ohci {
+       status = "okay";
+};
+
+&wmac {
+       ralink,mtd-eeprom = <&factory 0>;
+};