ralink: bump to the target to v4.3

[openwrt/svn-archive/archive.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / esw_rt3052.c

diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3052.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3052.c
index 247983b79e29f9b559cfaa4258b37fe6a97ced0b..e564dd81e5243a8de40f1174f62fe0a4a0d81cec 100644 (file)
--- a/target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3052.c
+++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3052.c
@@ -192,7 +192,6 @@
 #define RT5350_ESW_REG_PXTPC(_x)       (0x150 + (4 * _x))
 #define RT5350_EWS_REG_LED_POLARITY    0x168
 #define RT5350_RESET_EPHY              BIT(24)
-#define SYSC_REG_RESET_CTRL            0x34
 
 enum {
        /* Global attributes. */
@@ -512,9 +511,7 @@ static void esw_hw_init(struct rt305x_esw *esw)
 
        if (ralink_soc == RT305X_SOC_RT3352) {
                /* reset EPHY */
-               u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
-               rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
-               rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
+               fe_reset(RT5350_RESET_EPHY);
 
                rt305x_mii_write(esw, 0, 31, 0x8000);
                for (i = 0; i < 5; i++) {
@@ -563,9 +560,7 @@ static void esw_hw_init(struct rt305x_esw *esw)
                rt305x_mii_write(esw, 0, 31, 0x8000);
        } else if (ralink_soc == RT305X_SOC_RT5350) {
                /* reset EPHY */
-               u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
-               rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
-               rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
+               fe_reset(RT5350_RESET_EPHY);
 
                /* set the led polarity */
                esw_w32(esw, esw->reg_led_polarity & 0x1F, RT5350_EWS_REG_LED_POLARITY);
@@ -616,15 +611,13 @@ static void esw_hw_init(struct rt305x_esw *esw)
                rt305x_mii_write(esw, 0, 29, 0x598b);
                /* select local register */
                rt305x_mii_write(esw, 0, 31, 0x8000);
-       } else if (ralink_soc == MT762X_SOC_MT7628AN) {
+       } else if (ralink_soc == MT762X_SOC_MT7628AN || ralink_soc == MT762X_SOC_MT7688) {
                int i;
 //             u32 phy_val;
                u32 val;
 
                /* reset EPHY */
-               val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
-               rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
-               rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
+               fe_reset(RT5350_RESET_EPHY);
 
                rt305x_mii_write(esw, 0, 31, 0x2000); /* change G2 page */
                rt305x_mii_write(esw, 0, 26, 0x0020);
@@ -1049,7 +1042,7 @@ esw_get_port_tr_badgood(struct switch_dev *dev,
        int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16;
        u32 reg;
 
-       if ((ralink_soc != RT305X_SOC_RT5350) && (ralink_soc != MT762X_SOC_MT7628AN))
++      if ((ralink_soc != RT305X_SOC_RT5350) && (ralink_soc != MT762X_SOC_MT7628AN) && (ralink_soc != MT762X_SOC_MT7688))
                return -EINVAL;
 
        if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)