#include <linux/mii.h>
#include <linux/interrupt.h>
#include <linux/netdevice.h>
+#include <linux/dma-mapping.h>
#define NUM_RX_DESC 256
#define NUM_TX_DESC 256
#define RAMIPS_RX_CALC_IDX1 (RAMIPS_PDMA_OFFSET + 0x68)
#define RAMIPS_RX_DRX_IDX1 (RAMIPS_PDMA_OFFSET + 0x6C)
+/* MDIO_CFG register bits */
+#define RAMIPS_MDIO_CFG_AUTO_POLL_EN BIT(29)
+#define RAMIPS_MDIO_CFG_GP1_BP_EN BIT(16)
+#define RAMIPS_MDIO_CFG_GP1_FRC_EN BIT(15)
+#define RAMIPS_MDIO_CFG_GP1_SPEED_10 (0 << 13)
+#define RAMIPS_MDIO_CFG_GP1_SPEED_100 (1 << 13)
+#define RAMIPS_MDIO_CFG_GP1_SPEED_1000 (2 << 13)
+#define RAMIPS_MDIO_CFG_GP1_DUPLEX BIT(12)
+#define RAMIPS_MDIO_CFG_GP1_FC_TX BIT(11)
+#define RAMIPS_MDIO_CFG_GP1_FC_RX BIT(10)
+#define RAMIPS_MDIO_CFG_GP1_LNK_DWN BIT(9)
+#define RAMIPS_MDIO_CFG_GP1_AN_FAIL BIT(8)
+#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6)
+#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6)
+#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6)
+#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6)
+#define RAMIPS_MDIO_CFG_TURBO_MII_FREQ BIT(5)
+#define RAMIPS_MDIO_CFG_TURBO_MII_MODE BIT(4)
+#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2)
+#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2)
+#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2)
+#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2)
+#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_0 0
+#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_200 1
+#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_400 2
+#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_INV 3
+
/* uni-cast port */
#define RAMIPS_GDM1_ICS_EN BIT(22)
#define RAMIPS_GDM1_TCS_EN BIT(21)
#define RAMIPS_US_CYC_CNT_SHIFT 0x8
#define RAMIPS_US_CYC_CNT_DIVISOR 1000000
-#define RX_DMA_PLEN0(x) ((x >> 16) & 0x3fff)
+#define RX_DMA_PLEN0(_x) (((_x) >> 16) & 0x3fff)
#define RX_DMA_LSO BIT(30)
#define RX_DMA_DONE BIT(31)
unsigned int rxd2;
unsigned int rxd3;
unsigned int rxd4;
-};
+} __packed __aligned(4);
#define TX_DMA_PLEN0_MASK ((0x3fff) << 16)
-#define TX_DMA_PLEN0(x) ((x & 0x3fff) << 16)
+#define TX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
#define TX_DMA_LSO BIT(30)
#define TX_DMA_DONE BIT(31)
-#define TX_DMA_QN(x) (x << 16)
-#define TX_DMA_PN(x) (x << 24)
+#define TX_DMA_QN(_x) ((_x) << 16)
+#define TX_DMA_PN(_x) ((_x) << 24)
#define TX_DMA_QN_MASK TX_DMA_QN(0x7)
#define TX_DMA_PN_MASK TX_DMA_PN(0x7)
unsigned int txd2;
unsigned int txd3;
unsigned int txd4;
-};
+} __packed __aligned(4);
struct raeth_priv
{
- unsigned int phy_rx;
+ dma_addr_t rx_desc_dma;
struct tasklet_struct rx_tasklet;
struct ramips_rx_dma *rx;
struct sk_buff *rx_skb[NUM_RX_DESC];
+ dma_addr_t rx_dma[NUM_RX_DESC];
- unsigned int phy_tx;
+ dma_addr_t tx_desc_dma;
struct tasklet_struct tx_housekeeping_tasklet;
struct ramips_tx_dma *tx;
- struct sk_buff *tx_skb[NUM_RX_DESC];
+ struct sk_buff *tx_skb[NUM_TX_DESC];
unsigned int skb_free_idx;
spinlock_t page_lock;
+ struct net_device *netdev;
+ struct device *parent;
struct ramips_eth_platform_data *plat;
+
+ int link;
+ int speed;
+ int duplex;
+ int tx_fc;
+ int rx_fc;
+
+ struct mii_bus *mii_bus;
+ int mii_irq[PHY_MAX_ADDR];
+ struct phy_device *phy_dev;
+ spinlock_t phy_lock;
};
#endif /* RAMIPS_ETH_H */