ralink: set v3.10 as default

[openwrt/staging/lynxis/omap.git] / target / linux / ramips / patches-3.9 / 0139-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch

diff --git a/target/linux/ramips/patches-3.9/0139-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch b/target/linux/ramips/patches-3.9/0139-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch
deleted file mode 100644 (file)
index fb0cd7b..0000000
--- a/target/linux/ramips/patches-3.9/0139-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch
+++ /dev/null
@@ -1,20 +0,0 @@
-From 17d26ed75f0981cdc497f9062aec5f66d3c44d88 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Thu, 23 May 2013 18:46:25 +0200
-Subject: [PATCH 139/164] MIPS: ralink: add spi clock definition to mt7620a
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/mt7620.c |    1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -183,6 +183,7 @@ void __init ralink_clk_init(void)
-       ralink_clk_add("cpu", cpu_rate);
-       ralink_clk_add("10000100.timer", 40000000);
-       ralink_clk_add("10000500.uart", 40000000);
-+      ralink_clk_add("10000b00.spi", 40000000);
-       ralink_clk_add("10000c00.uartlite", 40000000);
- }
-