create mode 100644 arch/mips/ralink/malta-amon.c
create mode 100644 arch/mips/ralink/mt7621.c
-diff --git a/arch/mips/include/asm/mach-ralink/irq.h b/arch/mips/include/asm/mach-ralink/irq.h
-new file mode 100644
-index 0000000..4321865
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/irq.h
@@ -0,0 +1,9 @@
+#include_next <irq.h>
+
+#endif
-diff --git a/arch/mips/include/asm/mach-ralink/mt7621.h b/arch/mips/include/asm/mach-ralink/mt7621.h
-new file mode 100644
-index 0000000..21c8dc2
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/mt7621.h
-@@ -0,0 +1,39 @@
+@@ -0,0 +1,42 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+#ifndef _MT7621_REGS_H_
+#define _MT7621_REGS_H_
+
++#define MT7621_PALMBUS_BASE 0x1C000000
++#define MT7621_PALMBUS_SIZE 0x03FFFFFF
++
+#define MT7621_SYSC_BASE 0x1E000000
+
+#define SYSC_REG_CHIP_NAME0 0x00
+#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
+
+#endif
-diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c
-index b8ceee5..b97de1d 100644
---- a/arch/mips/kernel/mips-cm.c
-+++ b/arch/mips/kernel/mips-cm.c
-@@ -232,7 +232,7 @@ int mips_cm_probe(void)
- write_gcr_base(base_reg);
-
- /* disable CM regions */
-- write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
-+/* write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
- write_gcr_reg0_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
- write_gcr_reg1_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
- write_gcr_reg1_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
-@@ -240,7 +240,7 @@ int mips_cm_probe(void)
- write_gcr_reg2_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
- write_gcr_reg3_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
- write_gcr_reg3_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
--
-+*/
- /* probe for an L2-only sync region */
- mips_cm_probe_l2sync();
-
-diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S
-index 07d32a4..86c6284 100644
--- a/arch/mips/kernel/vmlinux.lds.S
+++ b/arch/mips/kernel/vmlinux.lds.S
@@ -51,6 +51,7 @@ SECTIONS
TEXT_TEXT
SCHED_TEXT
LOCK_TEXT
-diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
-index e9bc8c9..d078e61 100644
--- a/arch/mips/ralink/Kconfig
+++ b/arch/mips/ralink/Kconfig
@@ -12,6 +12,11 @@ config RALINK_ILL_ACC
choice
prompt "Ralink SoC selection"
default SOC_RT305X
-@@ -34,6 +39,15 @@ choice
+@@ -34,6 +39,16 @@ choice
config SOC_MT7620
bool "MT7620/8"
+ select MIPS_CPU_SCACHE
+ select SYS_SUPPORTS_MULTITHREADING
+ select SYS_SUPPORTS_SMP
-+ select SYS_SUPPORTS_MIPS_CMP
-+ select IRQ_GIC
++ select SYS_SUPPORTS_MIPS_CPS
++ select MIPS_GIC
++ select COMMON_CLK
++ select CLKSRC_MIPS_GIC
+ select HW_HAS_PCI
-+
endchoice
choice
-@@ -65,6 +79,10 @@ choice
+@@ -65,6 +80,10 @@ choice
depends on SOC_MT7620
select BUILTIN_DTB
endchoice
endif
-diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
-index a6c9d00..ca501db 100644
--- a/arch/mips/ralink/Makefile
+++ b/arch/mips/ralink/Makefile
-@@ -6,16 +6,21 @@
+@@ -6,16 +6,24 @@
# Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
# Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-obj-y := prom.o of.o reset.o clk.o irq.o timer.o
-+obj-y := prom.o of.o reset.o clk.o timer.o
++obj-y := prom.o of.o reset.o
++
++ifndef CONFIG_MIPS_GIC
++ obj-y += clk.o timer.o
++endif
obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o
+obj-$(CONFIG_IRQ_INTC) += irq.o
-+obj-$(CONFIG_IRQ_GIC) += irq-gic.o
-+obj-$(CONFIG_MIPS_MT_SMP) += malta-amon.o
++obj-$(CONFIG_MIPS_GIC) += irq-gic.o timer-gic.o
+
obj-$(CONFIG_SOC_RT288X) += rt288x.o
obj-$(CONFIG_SOC_RT305X) += rt305x.o
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
-diff --git a/arch/mips/ralink/Platform b/arch/mips/ralink/Platform
-index 6d9c8c4..6095fcc 100644
--- a/arch/mips/ralink/Platform
+++ b/arch/mips/ralink/Platform
-@@ -27,3 +27,8 @@ cflags-$(CONFIG_SOC_RT3883) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt
+@@ -27,3 +27,8 @@ cflags-$(CONFIG_SOC_RT3883) += -I$(srctr
#
load-$(CONFIG_SOC_MT7620) += 0xffffffff80000000
cflags-$(CONFIG_SOC_MT7620) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7620
+#
+load-$(CONFIG_SOC_MT7621) += 0xffffffff80001000
+cflags-$(CONFIG_SOC_MT7621) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7621
-diff --git a/arch/mips/ralink/irq-gic.c b/arch/mips/ralink/irq-gic.c
-new file mode 100644
-index 0000000..f1c541b
--- /dev/null
+++ b/arch/mips/ralink/irq-gic.c
-@@ -0,0 +1,268 @@
+@@ -0,0 +1,18 @@
+#include <linux/init.h>
-+#include <linux/sched.h>
-+#include <linux/slab.h>
-+#include <linux/interrupt.h>
-+#include <linux/kernel_stat.h>
-+#include <linux/hardirq.h>
-+#include <linux/preempt.h>
-+#include <linux/irqdomain.h>
-+#include <linux/of_platform.h>
-+#include <linux/of_address.h>
-+#include <linux/of_irq.h>
-+
-+#include <asm/irq_cpu.h>
-+#include <asm/mipsregs.h>
-+
-+#include <asm/irq.h>
-+#include <asm/setup.h>
-+
-+#include <asm/gic.h>
-+
-+#include <asm/mach-ralink/mt7621.h>
-+#define GIC_BASE_ADDR 0x1fbc0000
-+
-+unsigned long _gcmp_base;
-+static int gic_resched_int_base = 56;
-+static int gic_call_int_base = 60;
-+static struct irq_chip *irq_gic;
-+static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS];
-+
-+#if defined(CONFIG_MIPS_MT_SMP)
-+static int gic_resched_int_base;
-+static int gic_call_int_base;
-+
-+#define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu))
-+#define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu))
-+
-+static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
-+{
-+ scheduler_ipi();
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static irqreturn_t
-+ipi_call_interrupt(int irq, void *dev_id)
-+{
-+ smp_call_function_interrupt();
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static struct irqaction irq_resched = {
-+ .handler = ipi_resched_interrupt,
-+ .flags = IRQF_DISABLED|IRQF_PERCPU,
-+ .name = "ipi resched"
-+};
-+
-+static struct irqaction irq_call = {
-+ .handler = ipi_call_interrupt,
-+ .flags = IRQF_DISABLED|IRQF_PERCPU,
-+ .name = "ipi call"
-+};
-+
-+#endif
-+
-+static void __init
-+gic_fill_map(void)
-+{
-+ int i;
-+
-+ for (i = 0; i < ARRAY_SIZE(gic_intr_map); i++) {
-+ gic_intr_map[i].cpunum = 0;
-+ gic_intr_map[i].pin = GIC_CPU_INT0;
-+ gic_intr_map[i].polarity = GIC_POL_POS;
-+ gic_intr_map[i].trigtype = GIC_TRIG_LEVEL;
-+ gic_intr_map[i].flags = 0;
-+ }
-+
-+#if defined(CONFIG_MIPS_MT_SMP)
-+ {
-+ int cpu;
-+
-+ gic_call_int_base = ARRAY_SIZE(gic_intr_map) - nr_cpu_ids;
-+ gic_resched_int_base = gic_call_int_base - nr_cpu_ids;
-+
-+ i = gic_resched_int_base;
-+
-+ for (cpu = 0; cpu < nr_cpu_ids; cpu++) {
-+ gic_intr_map[i + cpu].cpunum = cpu;
-+ gic_intr_map[i + cpu].pin = GIC_CPU_INT1;
-+ gic_intr_map[i + cpu].trigtype = GIC_TRIG_EDGE;
-+
-+ gic_intr_map[i + cpu + nr_cpu_ids].cpunum = cpu;
-+ gic_intr_map[i + cpu + nr_cpu_ids].pin = GIC_CPU_INT2;
-+ gic_intr_map[i + cpu + nr_cpu_ids].trigtype = GIC_TRIG_EDGE;
-+ }
-+ }
-+#endif
-+}
-+
-+void
-+gic_irq_ack(struct irq_data *d)
-+{
-+ int irq = (d->irq - gic_irq_base);
-+
-+ GIC_CLR_INTR_MASK(irq);
-+
-+ if (gic_irq_flags[irq] & GIC_TRIG_EDGE)
-+ GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
-+}
-+
-+void
-+gic_finish_irq(struct irq_data *d)
-+{
-+ GIC_SET_INTR_MASK(d->irq - gic_irq_base);
-+}
-+
-+void __init
-+gic_platform_init(int irqs, struct irq_chip *irq_controller)
-+{
-+ irq_gic = irq_controller;
-+}
-+
-+static void
-+gic_irqdispatch(void)
-+{
-+ unsigned int irq = gic_get_int();
-+
-+ if (likely(irq < GIC_NUM_INTRS))
-+ do_IRQ(MIPS_GIC_IRQ_BASE + irq);
-+ else {
-+ pr_debug("Spurious GIC Interrupt!\n");
-+ spurious_interrupt();
-+ }
-+
-+}
-+
-+static void
-+vi_timer_irqdispatch(void)
-+{
-+ do_IRQ(cp0_compare_irq);
-+}
-+
-+#if defined(CONFIG_MIPS_MT_SMP)
-+unsigned int
-+plat_ipi_call_int_xlate(unsigned int cpu)
-+{
-+ return GIC_CALL_INT(cpu);
-+}
-+
-+unsigned int
-+plat_ipi_resched_int_xlate(unsigned int cpu)
-+{
-+ return GIC_RESCHED_INT(cpu);
-+}
-+#endif
-+
-+asmlinkage void
-+plat_irq_dispatch(void)
-+{
-+ unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
+
-+ if (unlikely(!pending)) {
-+ pr_err("Spurious CP0 Interrupt!\n");
-+ spurious_interrupt();
-+ } else {
-+ if (pending & CAUSEF_IP7)
-+ do_IRQ(cp0_compare_irq);
++#include <linux/of.h>
++#include <linux/irqchip.h>
++#include <linux/irqchip/mips-gic.h>
+
-+ if (pending & (CAUSEF_IP4 | CAUSEF_IP3 | CAUSEF_IP2))
-+ gic_irqdispatch();
-+ }
-+}
-+
-+unsigned int __cpuinit
-+get_c0_compare_int(void)
++int get_c0_perfcount_int(void)
+{
-+ return CP0_LEGACY_COMPARE_IRQ;
-+}
-+
-+static int
-+gic_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
-+{
-+ irq_set_chip_and_handler(irq, irq_gic,
-+#if defined(CONFIG_MIPS_MT_SMP)
-+ (hw >= gic_resched_int_base) ?
-+ handle_percpu_irq :
-+#endif
-+ handle_level_irq);
-+
-+ return 0;
++ return gic_get_c0_perfcount_int();
+}
-+
-+static const struct irq_domain_ops irq_domain_ops = {
-+ .xlate = irq_domain_xlate_onecell,
-+ .map = gic_map,
-+};
-+
-+static int __init
-+of_gic_init(struct device_node *node,
-+ struct device_node *parent)
-+{
-+ struct irq_domain *domain;
-+ struct resource gcmp = { 0 }, gic = { 0 };
-+ unsigned int gic_rev;
-+ int i;
-+
-+ if (of_address_to_resource(node, 0, &gic))
-+ panic("Failed to get gic memory range");
-+ if (request_mem_region(gic.start, resource_size(&gic),
-+ gic.name) < 0)
-+ panic("Failed to request gic memory");
-+ if (of_address_to_resource(node, 2, &gcmp))
-+ panic("Failed to get gic memory range");
-+ if (request_mem_region(gcmp.start, resource_size(&gcmp),
-+ gcmp.name) < 0)
-+ panic("Failed to request gcmp memory");
-+
-+ _gcmp_base = (unsigned long) ioremap_nocache(gcmp.start, resource_size(&gcmp));
-+ if (!_gcmp_base)
-+ panic("Failed to remap gcmp memory\n");
-+
-+ /* tell the gcmp where to find the gic */
-+ write_gcr_gic_base(GIC_BASE_ADDR | CM_GCR_GIC_BASE_GICEN_MSK);
-+ gic_present = 1;
-+ if (cpu_has_vint) {
-+ set_vi_handler(2, gic_irqdispatch);
-+ set_vi_handler(3, gic_irqdispatch);
-+ set_vi_handler(4, gic_irqdispatch);
-+ set_vi_handler(7, vi_timer_irqdispatch);
-+ }
-+
-+ gic_fill_map();
-+
-+ gic_init(gic.start, resource_size(&gic), gic_intr_map,
-+ ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
-+
-+ GICREAD(GIC_REG(SHARED, GIC_SH_REVISIONID), gic_rev);
-+ pr_info("gic: revision %d.%d\n", (gic_rev >> 8) & 0xff, gic_rev & 0xff);
-+
-+ domain = irq_domain_add_legacy(node, GIC_NUM_INTRS, MIPS_GIC_IRQ_BASE,
-+ 0, &irq_domain_ops, NULL);
-+ if (!domain)
-+ panic("Failed to add irqdomain");
-+
-+#if defined(CONFIG_MIPS_MT_SMP)
-+ for (i = 0; i < nr_cpu_ids; i++) {
-+ setup_irq(MIPS_GIC_IRQ_BASE + GIC_RESCHED_INT(i), &irq_resched);
-+ setup_irq(MIPS_GIC_IRQ_BASE + GIC_CALL_INT(i), &irq_call);
-+ }
-+#endif
-+
-+ change_c0_status(ST0_IM, STATUSF_IP7 | STATUSF_IP4 | STATUSF_IP3 |
-+ STATUSF_IP2);
-+ return 0;
-+}
-+
-+static struct of_device_id __initdata of_irq_ids[] = {
-+ { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_intc_init },
-+ { .compatible = "ralink,mt7621-gic", .data = of_gic_init },
-+ {},
-+};
++EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
+
+void __init
+arch_init_irq(void)
+{
-+ of_irq_init(of_irq_ids);
++ irqchip_init();
+}
-diff --git a/arch/mips/ralink/malta-amon.c b/arch/mips/ralink/malta-amon.c
-new file mode 100644
-index 0000000..1e47844
---- /dev/null
-+++ b/arch/mips/ralink/malta-amon.c
-@@ -0,0 +1,81 @@
-+/*
-+ * Copyright (C) 2007 MIPS Technologies, Inc.
-+ * All rights reserved.
-+
-+ * This program is free software; you can distribute it and/or modify it
-+ * under the terms of the GNU General Public License (Version 2) as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-+ * for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-+ *
-+ * Arbitrary Monitor interface
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/smp.h>
+
-+#include <asm/addrspace.h>
-+#include <asm/mips-boards/launch.h>
-+#include <asm/mipsmtregs.h>
-+
-+int amon_cpu_avail(int cpu)
-+{
-+ struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
-+
-+ if (cpu < 0 || cpu >= NCPULAUNCH) {
-+ pr_debug("avail: cpu%d is out of range\n", cpu);
-+ return 0;
-+ }
-+
-+ launch += cpu;
-+ if (!(launch->flags & LAUNCH_FREADY)) {
-+ pr_debug("avail: cpu%d is not ready\n", cpu);
-+ return 0;
-+ }
-+ if (launch->flags & (LAUNCH_FGO|LAUNCH_FGONE)) {
-+ pr_debug("avail: too late.. cpu%d is already gone\n", cpu);
-+ return 0;
-+ }
-+
-+ return 1;
-+}
-+
-+void amon_cpu_start(int cpu,
-+ unsigned long pc, unsigned long sp,
-+ unsigned long gp, unsigned long a0)
-+{
-+ volatile struct cpulaunch *launch =
-+ (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
-+
-+ if (!amon_cpu_avail(cpu))
-+ return;
-+ if (cpu == smp_processor_id()) {
-+ pr_debug("launch: I am cpu%d!\n", cpu);
-+ return;
-+ }
-+ launch += cpu;
-+
-+ pr_debug("launch: starting cpu%d\n", cpu);
-+
-+ launch->pc = pc;
-+ launch->gp = gp;
-+ launch->sp = sp;
-+ launch->a0 = a0;
-+
-+ smp_wmb(); /* Target must see parameters before go */
-+ launch->flags |= LAUNCH_FGO;
-+ smp_wmb(); /* Target must see go before we poll */
-+
-+ while ((launch->flags & LAUNCH_FGONE) == 0)
-+ ;
-+ smp_rmb(); /* Target will be updating flags soon */
-+ pr_debug("launch: cpu%d gone!\n", cpu);
-+}
-diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c
-new file mode 100644
-index 0000000..c28743b
--- /dev/null
+++ b/arch/mips/ralink/mt7621.c
-@@ -0,0 +1,209 @@
+@@ -0,0 +1,223 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ { 0 }
+};
+
++phys_addr_t mips_cpc_default_phys_base() {
++ panic("Cannot detect cpc address");
++}
++
+void __init ralink_clk_init(void)
+{
+ int cpu_fdiv = 0;
+ }
+ break;
+ }
-+ cpu_clk = 880000000;
-+ ralink_clk_add("cpu", cpu_clk);
-+ ralink_clk_add("1e000b00.spi", 50000000);
-+ ralink_clk_add("1e000c00.uartlite", 50000000);
-+ ralink_clk_add("1e000d00.uart", 50000000);
+}
+
+void __init ralink_of_remap(void)
+ mips_cm_probe();
+ mips_cpc_probe();
+
++ if (mips_cm_numiocu()) {
++ /* mips_cm_probe() wipes out bootloader
++ config for CM regions and we have to configure them
++ again. This SoC cannot talk to pamlbus devices
++ witout proper iocu region set up.
++
++ FIXME: it would be better to do this with values
++ from DT, but we need this very early because
++ without this we cannot talk to pretty much anything
++ including serial.
++ */
++ write_gcr_reg0_base(MT7621_PALMBUS_BASE);
++ write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE | CM_GCR_REGn_MASK_CMTGT_IOCU0);
++ }
++
+ if (!register_cps_smp_ops())
+ return;
+ if (!register_cmp_smp_ops())
+ if (!register_vsmp_smp_ops())
+ return;
+}
---
-1.7.10.4
-
+--- /dev/null
++++ b/arch/mips/ralink/timer-gic.c
+@@ -0,0 +1,15 @@
++#include <linux/init.h>
++
++#include <linux/of.h>
++#include <linux/clk-provider.h>
++#include <linux/clocksource.h>
++
++#include "common.h"
++
++void __init plat_time_init(void)
++{
++ ralink_of_remap();
++
++ of_clk_init(NULL);
++ clocksource_of_init();
++}
projects / openwrt / openwrt.git / blobdiff