ramips: switch to Linux 6.6

[openwrt/staging/stintel.git] / target / linux / ramips / patches-6.1 / 005-v6.5-03-mips-ralink-rt288x-remove-clock-related-code.patch

diff --git a/target/linux/ramips/patches-6.1/005-v6.5-03-mips-ralink-rt288x-remove-clock-related-code.patch b/target/linux/ramips/patches-6.1/005-v6.5-03-mips-ralink-rt288x-remove-clock-related-code.patch
deleted file mode 100644 (file)
index df4208b..0000000
--- a/target/linux/ramips/patches-6.1/005-v6.5-03-mips-ralink-rt288x-remove-clock-related-code.patch
+++ /dev/null
@@ -1,81 +0,0 @@
-From ffcdf47379eae86dc8f8f02c62994dacf2c9038e Mon Sep 17 00:00:00 2001
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Mon, 19 Jun 2023 06:09:35 +0200
-Subject: [PATCH 3/9] mips: ralink: rt288x: remove clock related code
-
-A properly clock driver for ralink SoCs has been added. Hence there is no
-need to have clock related code in 'arch/mips/ralink' folder anymore.
-
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/include/asm/mach-ralink/rt288x.h | 10 ----------
- arch/mips/ralink/rt288x.c                  | 31 ------------------------------
- 2 files changed, 41 deletions(-)
-
---- a/arch/mips/include/asm/mach-ralink/rt288x.h
-+++ b/arch/mips/include/asm/mach-ralink/rt288x.h
-@@ -17,7 +17,6 @@
- #define SYSC_REG_CHIP_NAME1           0x04
- #define SYSC_REG_CHIP_ID              0x0c
- #define SYSC_REG_SYSTEM_CONFIG                0x10
--#define SYSC_REG_CLKCFG                       0x30
- 
- #define RT2880_CHIP_NAME0             0x38325452
- #define RT2880_CHIP_NAME1             0x20203038
-@@ -26,15 +25,6 @@
- #define CHIP_ID_ID_SHIFT              8
- #define CHIP_ID_REV_MASK              0xff
- 
--#define SYSTEM_CONFIG_CPUCLK_SHIFT    20
--#define SYSTEM_CONFIG_CPUCLK_MASK     0x3
--#define SYSTEM_CONFIG_CPUCLK_250      0x0
--#define SYSTEM_CONFIG_CPUCLK_266      0x1
--#define SYSTEM_CONFIG_CPUCLK_280      0x2
--#define SYSTEM_CONFIG_CPUCLK_300      0x3
--
--#define CLKCFG_SRAM_CS_N_WDT          BIT(9)
--
- #define RT2880_SDRAM_BASE             0x08000000
- #define RT2880_MEM_SIZE_MIN           2
- #define RT2880_MEM_SIZE_MAX           128
---- a/arch/mips/ralink/rt288x.c
-+++ b/arch/mips/ralink/rt288x.c
-@@ -17,37 +17,6 @@
- 
- #include "common.h"
- 
--void __init ralink_clk_init(void)
--{
--      unsigned long cpu_rate, wmac_rate = 40000000;
--      u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
--      t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
--
--      switch (t) {
--      case SYSTEM_CONFIG_CPUCLK_250:
--              cpu_rate = 250000000;
--              break;
--      case SYSTEM_CONFIG_CPUCLK_266:
--              cpu_rate = 266666667;
--              break;
--      case SYSTEM_CONFIG_CPUCLK_280:
--              cpu_rate = 280000000;
--              break;
--      case SYSTEM_CONFIG_CPUCLK_300:
--              cpu_rate = 300000000;
--              break;
--      }
--
--      ralink_clk_add("cpu", cpu_rate);
--      ralink_clk_add("300100.timer", cpu_rate / 2);
--      ralink_clk_add("300120.watchdog", cpu_rate / 2);
--      ralink_clk_add("300500.uart", cpu_rate / 2);
--      ralink_clk_add("300900.i2c", cpu_rate / 2);
--      ralink_clk_add("300c00.uartlite", cpu_rate / 2);
--      ralink_clk_add("400000.ethernet", cpu_rate / 2);
--      ralink_clk_add("480000.wmac", wmac_rate);
--}
--
- void __init ralink_of_remap(void)
- {
-       rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc");