ramips: switch to Linux 6.6

[openwrt/staging/stintel.git] / target / linux / ramips / patches-6.1 / 320-MIPS-add-support-for-buggy-MT7621S-core-detection.patch

diff --git a/target/linux/ramips/patches-6.1/320-MIPS-add-support-for-buggy-MT7621S-core-detection.patch b/target/linux/ramips/patches-6.1/320-MIPS-add-support-for-buggy-MT7621S-core-detection.patch
deleted file mode 100644 (file)
index ef54835..0000000
--- a/target/linux/ramips/patches-6.1/320-MIPS-add-support-for-buggy-MT7621S-core-detection.patch
+++ /dev/null
@@ -1,75 +0,0 @@
-From 6decd1aad15f56b169217789630a0098b496de0e Mon Sep 17 00:00:00 2001
-From: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
-Date: Wed, 7 Apr 2021 13:07:38 -0700
-Subject: [PATCH] MIPS: add support for buggy MT7621S core detection
-
-Most MT7621 SoCs have 2 cores, which is detected and supported properly
-by CPS.
-
-Unfortunately, MT7621 SoC has a less common S variant with only one core.
-On MT7621S, GCR_CONFIG still reports 2 cores, which leads to hangs when
-starting SMP. CPULAUNCH registers can be used in that case to detect the
-absence of the second core and override the GCR_CONFIG PCORES field.
-
-Rework a long-standing OpenWrt patch to override the value of
-mips_cps_numcores on single-core MT7621 systems.
-
-Tested on a dual-core MT7621 device (Ubiquiti ER-X) and a single-core
-MT7621 device (Netgear R6220).
-
-Original 4.14 OpenWrt patch:
-Link: https://git.openwrt.org/?p=openwrt/openwrt.git;a=commitdiff;h=4cdbc90a376dd0555201c1434a2081e055e9ceb7
-Current 5.10 OpenWrt patch:
-Link: https://git.openwrt.org/?p=openwrt/openwrt.git;a=blob;f=target/linux/ramips/patches-5.10/320-mt7621-core-detect-hack.patch;h=c63f0f4c1ec742e24d8480e80553863744b58f6a;hb=10267e17299806f9885d086147878f6c492cb904
-
-Suggested-by: Felix Fietkau <nbd@nbd.name>
-Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/include/asm/mips-cps.h | 23 ++++++++++++++++++++++-
- 1 file changed, 22 insertions(+), 1 deletion(-)
-
---- a/arch/mips/include/asm/mips-cps.h
-+++ b/arch/mips/include/asm/mips-cps.h
-@@ -11,6 +11,8 @@
- #include <linux/io.h>
- #include <linux/types.h>
- 
-+#include <asm/mips-boards/launch.h>
-+
- extern unsigned long __cps_access_bad_size(void)
-       __compiletime_error("Bad size for CPS accessor");
- 
-@@ -162,12 +164,31 @@ static inline uint64_t mips_cps_cluster_
-  */
- static inline unsigned int mips_cps_numcores(unsigned int cluster)
- {
-+      unsigned int ncores;
-+
-       if (!mips_cm_present())
-               return 0;
- 
-       /* Add one before masking to handle 0xff indicating no cores */
--      return FIELD_GET(CM_GCR_CONFIG_PCORES,
-+      ncores = FIELD_GET(CM_GCR_CONFIG_PCORES,
-                        mips_cps_cluster_config(cluster) + 1);
-+
-+      if (IS_ENABLED(CONFIG_SOC_MT7621)) {
-+              struct cpulaunch *launch;
-+
-+              /*
-+               * Ralink MT7621S SoC is single core, but the GCR_CONFIG method
-+               * always reports 2 cores. Check the second core's LAUNCH_FREADY
-+               * flag to detect if the second core is missing. This method
-+               * only works before the core has been started.
-+               */
-+              launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
-+              launch += 2; /* MT7621 has 2 VPEs per core */
-+              if (!(launch->flags & LAUNCH_FREADY))
-+                      ncores = 1;
-+      }
-+
-+      return ncores;
- }
- 
- /**