ramips: 6.6: remove old patches

[openwrt/staging/stintel.git] / target / linux / ramips / patches-6.6 / 005-v6.5-08-mips-ralink-get-cpu-rate-from-new-driver-code.patch

diff --git a/target/linux/ramips/patches-6.6/005-v6.5-08-mips-ralink-get-cpu-rate-from-new-driver-code.patch b/target/linux/ramips/patches-6.6/005-v6.5-08-mips-ralink-get-cpu-rate-from-new-driver-code.patch
deleted file mode 100644 (file)
index 2430c1f..0000000
--- a/target/linux/ramips/patches-6.6/005-v6.5-08-mips-ralink-get-cpu-rate-from-new-driver-code.patch
+++ /dev/null
@@ -1,102 +0,0 @@
-From ad38c17b0c26ae2108b50ac1eb0281a2e1ce08e9 Mon Sep 17 00:00:00 2001
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Mon, 19 Jun 2023 06:09:40 +0200
-Subject: [PATCH 8/9] mips: ralink: get cpu rate from new driver code
-
-At very early stage on boot, there is a need to set 'mips_hpt_frequency'.
-This timer frequency is a half of the CPU frequency. To get clocks properly
-set we need to call to 'of_clk_init()' and properly get cpu clock frequency
-afterwards. Depending on the SoC, CPU clock index and compatible differs, so
-use them to get the proper clock frm the clock provider. Hence, adapt code
-to be aligned with new clock driver.
-
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/ralink/clk.c | 61 ++++++++++++++++++++++++++++++++++++++++++--------
- 1 file changed, 52 insertions(+), 9 deletions(-)
-
---- a/arch/mips/ralink/clk.c
-+++ b/arch/mips/ralink/clk.c
-@@ -11,29 +11,72 @@
- #include <linux/clkdev.h>
- #include <linux/clk.h>
- #include <linux/clk-provider.h>
-+#include <asm/mach-ralink/ralink_regs.h>
- 
- #include <asm/time.h>
- 
- #include "common.h"
- 
--void ralink_clk_add(const char *dev, unsigned long rate)
-+static const char *clk_cpu(int *idx)
- {
--      struct clk *clk = clk_register_fixed_rate(NULL, dev, NULL, 0, rate);
--
--      if (!clk)
--              panic("failed to add clock");
--
--      clkdev_create(clk, NULL, "%s", dev);
-+      switch (ralink_soc) {
-+      case RT2880_SOC:
-+              *idx = 0;
-+              return "ralink,rt2880-sysc";
-+      case RT3883_SOC:
-+              *idx = 0;
-+              return "ralink,rt3883-sysc";
-+      case RT305X_SOC_RT3050:
-+              *idx = 0;
-+              return "ralink,rt3050-sysc";
-+      case RT305X_SOC_RT3052:
-+              *idx = 0;
-+              return "ralink,rt3052-sysc";
-+      case RT305X_SOC_RT3350:
-+              *idx = 1;
-+              return "ralink,rt3350-sysc";
-+      case RT305X_SOC_RT3352:
-+              *idx = 1;
-+              return "ralink,rt3352-sysc";
-+      case RT305X_SOC_RT5350:
-+              *idx = 1;
-+              return "ralink,rt5350-sysc";
-+      case MT762X_SOC_MT7620A:
-+              *idx = 2;
-+              return "ralink,mt7620-sysc";
-+      case MT762X_SOC_MT7620N:
-+              *idx = 2;
-+              return "ralink,mt7620-sysc";
-+      case MT762X_SOC_MT7628AN:
-+              *idx = 1;
-+              return "ralink,mt7628-sysc";
-+      case MT762X_SOC_MT7688:
-+              *idx = 1;
-+              return "ralink,mt7688-sysc";
-+      default:
-+              *idx = -1;
-+              return "invalid";
-+      }
- }
- 
- void __init plat_time_init(void)
- {
-+      struct of_phandle_args clkspec;
-+      const char *compatible;
-       struct clk *clk;
-+      int cpu_clk_idx;
- 
-       ralink_of_remap();
- 
--      ralink_clk_init();
--      clk = clk_get_sys("cpu", NULL);
-+      compatible = clk_cpu(&cpu_clk_idx);
-+      if (cpu_clk_idx == -1)
-+              panic("unable to get CPU clock index");
-+
-+      of_clk_init(NULL);
-+      clkspec.np = of_find_compatible_node(NULL, NULL, compatible);
-+      clkspec.args_count = 1;
-+      clkspec.args[0] = cpu_clk_idx;
-+      clk = of_clk_get_from_provider(&clkspec);
-       if (IS_ERR(clk))
-               panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
-       pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);