realtek: clock driver: add switch clock

[openwrt/staging/svanheule.git] / target / linux / realtek / files-5.10 / drivers / clk / realtek / clk-rtl83xx.h

diff --git a/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.h b/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.h
index 015d15572b9f98b4d148a120dde645243769cdac..4e2afee911c5dde1aa683ade2d2ca2c5fb7ac9b7 100644 (file)
--- a/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.h
+++ b/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.h
@@ -14,18 +14,29 @@
 #define RTL838X_PLL_GLB_CTRL                   (0x0fc0)
 #define RTL838X_PLL_CPU_CTRL0                  (0x0fc4)
 #define RTL838X_PLL_CPU_CTRL1                  (0x0fc8)
+#define RTL838X_PLL_CPU_MISC_CTRL              (0x0fcc)
 #define RTL838X_PLL_LXB_CTRL0                  (0x0fd0)
 #define RTL838X_PLL_LXB_CTRL1                  (0x0fd4)
+#define RTL838X_PLL_LXB_MISC_CTRL              (0x0fd8)
 #define RTL838X_PLL_MEM_CTRL0                  (0x0fdc)
 #define RTL838X_PLL_MEM_CTRL1                  (0x0fe0)
+#define RTL838X_PLL_MEM_MISC_CTRL              (0x0fe4)
+#define RTL838X_PLL_SW_CTRL0                   (0x0fe8)
+#define RTL838X_PLL_SW_CTRL1                   (0x0fec)
+#define RTL838X_PLL_SW_MISC_CTRL               (0x0ff0)
 
 #define RTL839X_PLL_GLB_CTRL                   (0x0024)
 #define RTL839X_PLL_CPU_CTRL0                  (0x0028)
 #define RTL839X_PLL_CPU_CTRL1                  (0x002c)
+#define RTL839X_PLL_CPU_MISC_CTRL              (0x0034)
 #define RTL839X_PLL_LXB_CTRL0                  (0x0038)
 #define RTL839X_PLL_LXB_CTRL1                  (0x003c)
+#define RTL839X_PLL_LXB_MISC_CTRL              (0x0044)
 #define RTL839X_PLL_MEM_CTRL0                  (0x0048)
 #define RTL839X_PLL_MEM_CTRL1                  (0x004c)
+#define RTL839X_PLL_MEM_MISC_CTRL              (0x0054)
+#define RTL839X_PLL_SW_CTRL                    (0x0058)
+#define RTL839X_PLL_SW_MISC_CTRL               (0x005c)
 
 #define RTL_PLL_CTRL0_CMU_SEL_PREDIV(v)                (((v) >> 0) & 0x3)
 #define RTL_PLL_CTRL0_CMU_SEL_DIV4(v)          (((v) >> 2) & 0x1)