rockchip: add NanoPi R5S support

[openwrt/staging/hauke.git] / target / linux / rockchip / patches-6.1 / 011-v6.4-arm64-dts-rockchip-fix-gmac-support-for-NanoPi-R5S.patch

diff --git a/target/linux/rockchip/patches-6.1/011-v6.4-arm64-dts-rockchip-fix-gmac-support-for-NanoPi-R5S.patch b/target/linux/rockchip/patches-6.1/011-v6.4-arm64-dts-rockchip-fix-gmac-support-for-NanoPi-R5S.patch
new file mode 100644 (file)
index 0000000..47f76d5
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/011-v6.4-arm64-dts-rockchip-fix-gmac-support-for-NanoPi-R5S.patch
@@ -0,0 +1,49 @@
+From 31425b1fadb2040b359e52ffc24c049a78d56c96 Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Sat, 18 Mar 2023 16:37:44 +0800
+Subject: [PATCH] arm64: dts: rockchip: fix gmac support for NanoPi R5S
+
+- Changed phy-mode to rgmii.
+
+- Fixed pull type in pinctrl for gmac0.
+
+- Removed duplicate properties in mdio node.
+  These properties are defined in the gmac0 node already.
+
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+Link: https://lore.kernel.org/r/20230318083745.6181-5-cnsztl@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 7 ++-----
+ 1 file changed, 2 insertions(+), 5 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
+@@ -57,7 +57,7 @@
+       assigned-clock-rates = <0>, <125000000>;
+       clock_in_out = "output";
+       phy-handle = <&rgmii_phy0>;
+-      phy-mode = "rgmii-id";
++      phy-mode = "rgmii";
+       pinctrl-names = "default";
+       pinctrl-0 = <&gmac0_miim
+                    &gmac0_tx_bus2
+@@ -79,9 +79,6 @@
+               reg = <1>;
+               pinctrl-0 = <&eth_phy0_reset_pin>;
+               pinctrl-names = "default";
+-              reset-assert-us = <10000>;
+-              reset-deassert-us = <50000>;
+-              reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
+       };
+ };
+ 
+@@ -115,7 +112,7 @@
+ &pinctrl {
+       gmac0 {
+               eth_phy0_reset_pin: eth-phy0-reset-pin {
+-                      rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
++                      rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
+               };
+       };
+