sifiveu: copy patches from 5.15 to 6.1

[openwrt/staging/wigyori.git] / target / linux / sifiveu / patches-6.1 / 0001-riscv-sifive-fu740-cpu-1-2-3-4-set-compatible-to-sif.patch

diff --git a/target/linux/sifiveu/patches-6.1/0001-riscv-sifive-fu740-cpu-1-2-3-4-set-compatible-to-sif.patch b/target/linux/sifiveu/patches-6.1/0001-riscv-sifive-fu740-cpu-1-2-3-4-set-compatible-to-sif.patch
new file mode 100644 (file)
index 0000000..9a1c968
--- /dev/null
+++ b/target/linux/sifiveu/patches-6.1/0001-riscv-sifive-fu740-cpu-1-2-3-4-set-compatible-to-sif.patch
@@ -0,0 +1,49 @@
+From ab5c8f5492cce16ff2104393e2f1fa64a3ff6e88 Mon Sep 17 00:00:00 2001
+From: David Abdurachmanov <david.abdurachmanov@sifive.com>
+Date: Wed, 17 Feb 2021 06:06:14 -0800
+Subject: [PATCH 1/7] riscv: sifive: fu740: cpu{1,2,3,4} set compatible to
+ sifive,u74-mc
+
+Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
+---
+ arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
++++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
+@@ -39,7 +39,7 @@
+                       };
+               };
+               cpu1: cpu@1 {
+-                      compatible = "sifive,bullet0", "riscv";
++                      compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
+                       d-cache-block-size = <64>;
+                       d-cache-sets = <64>;
+                       d-cache-size = <32768>;
+@@ -63,7 +63,7 @@
+                       };
+               };
+               cpu2: cpu@2 {
+-                      compatible = "sifive,bullet0", "riscv";
++                      compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
+                       d-cache-block-size = <64>;
+                       d-cache-sets = <64>;
+                       d-cache-size = <32768>;
+@@ -87,7 +87,7 @@
+                       };
+               };
+               cpu3: cpu@3 {
+-                      compatible = "sifive,bullet0", "riscv";
++                      compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
+                       d-cache-block-size = <64>;
+                       d-cache-sets = <64>;
+                       d-cache-size = <32768>;
+@@ -111,7 +111,7 @@
+                       };
+               };
+               cpu4: cpu@4 {
+-                      compatible = "sifive,bullet0", "riscv";
++                      compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
+                       d-cache-block-size = <64>;
+                       d-cache-sets = <64>;
+                       d-cache-size = <32768>;