rename and renumber storm patches

[openwrt/svn-archive/archive.git] / target / linux / storm / patches / 004-gmac_enable_napi.patch

diff --git a/target/linux/storm/patches/004-gmac_enable_napi.patch b/target/linux/storm/patches/004-gmac_enable_napi.patch
new file mode 100644 (file)
index 0000000..ea374c4
--- /dev/null
+++ b/target/linux/storm/patches/004-gmac_enable_napi.patch
@@ -0,0 +1,81 @@
+--- a/drivers/net/sl351x_gmac.c
++++ b/drivers/net/sl351x_gmac.c
+@@ -68,9 +68,11 @@
+ #include <linux/ip.h>
+ #endif
+ 
++/* Enables NAPI unconditionally */
++#define CONFIG_SL_NAPI                                        1
++
+ // #define SL351x_TEST_WORKAROUND
+ #ifdef CONFIG_SL351x_NAT
+-#define CONFIG_SL_NAPI                                        1
+ #endif
+ #define GMAX_TX_INTR_DISABLED                 1
+ #define DO_HW_CHKSUM                                  1
+@@ -124,12 +126,17 @@
+  *************************************************************/
+ static int    gmac_initialized = 0;
+ TOE_INFO_T toe_private_data;
+-//static int          do_again = 0;
++static int            do_again = 0;
+ spinlock_t gmac_fq_lock;
+ unsigned int FLAG_SWITCH;
+ 
+ static unsigned int           next_tick = 3 * HZ;
+-static unsigned char          eth_mac[CONFIG_MAC_NUM][6]= {{0x00,0x11,0x11,0x87,0x87,0x87}, {0x00,0x22,0x22,0xab,0xab,0xab}};
++static unsigned char          eth_mac[CONFIG_MAC_NUM][6]= {
++              {0x00,0x11,0x11,0x87,0x87,0x87},
++#if GMAC_NUM != 1
++              {0x00,0x22,0x22,0xab,0xab,0xab}
++#endif
++};
+ 
+ #undef CONFIG_SL351x_RXTOE
+ extern NAT_CFG_T nat_cfg;
+@@ -2443,7 +2450,8 @@
+       toe = (TOE_INFO_T *)&toe_private_data;
+ //    handle NAPI
+ #ifdef CONFIG_SL_NAPI
+-if (storlink_ctl.pauseoff == 1)
++      /* XXX: check this, changed from 'storlink_ctl.pauseoff == 1' to if (1) */
++if (1)
+ {
+ /* disable GMAC interrupt */
+     //toe_gmac_disable_interrupt(tp->irq);
+@@ -2530,7 +2538,7 @@
+                               {
+                                       if (likely(netif_rx_schedule_prep(dev)))
+                               {
+-                                      unsigned int data32;
++                                      // unsigned int data32;
+                                       // disable GMAC-0 rx interrupt
+                                       // class-Q & TOE-Q are implemented in future
+                                       //data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
+@@ -2563,7 +2571,7 @@
+                       {
+                               if (likely(netif_rx_schedule_prep(dev)))
+                       {
+-                              unsigned int data32;
++                              // unsigned int data32;
+                               // disable GMAC-0 rx interrupt
+                               // class-Q & TOE-Q are implemented in future
+                               //data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
+@@ -4217,7 +4225,7 @@
+       GMAC_INFO_T                     *tp = (GMAC_INFO_T *)dev->priv;
+       unsigned int            status4;
+       volatile DMA_RWPTR_T    fq_rwptr;
+-      int                                     max_cnt = TOE_SW_FREEQ_DESC_NUM;//TOE_SW_FREEQ_DESC_NUM = 64
++      // int                                  max_cnt = TOE_SW_FREEQ_DESC_NUM;//TOE_SW_FREEQ_DESC_NUM = 64
+       //unsigned long         rx_old_bytes;
+       struct net_device_stats *isPtr = (struct net_device_stats *)&tp->ifStatics;
+       //unsigned long long    rx_time;
+@@ -4479,7 +4487,7 @@
+ 
+       if (rwptr.bits.rptr == rwptr.bits.wptr)
+       {
+-              unsigned int data32;
++              // unsigned int data32;
+                       //printk("%s:---[rwptr.bits.rptr == rwptr.bits.wptr]   rx_pkts_num=%d------rwptr.bits.rptr=0x%x------->Default_Q [rwptr.bits.rptr(SW)=0x%x,   rwptr.bits.wptr(HW) = 0x%x ]---->Free_Q(SW_HW) = 0x%8x \n",__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.rptr,rwptr.bits.wptr,fq_rwptr.bits32 );
+ 
+           /* Receive descriptor is empty now */