sunxi: remove 3.13 support

[openwrt/svn-archive/archive.git] / target / linux / sunxi / patches-3.13 / 119-dt-sunxi-add-pll5-pll6.patch

diff --git a/target/linux/sunxi/patches-3.13/119-dt-sunxi-add-pll5-pll6.patch b/target/linux/sunxi/patches-3.13/119-dt-sunxi-add-pll5-pll6.patch
deleted file mode 100644 (file)
index db0020e..0000000
--- a/target/linux/sunxi/patches-3.13/119-dt-sunxi-add-pll5-pll6.patch
+++ /dev/null
@@ -1,187 +0,0 @@
-From 6d3ca59232090bff1b5e1abfd3417a3859e47425 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Mon, 23 Dec 2013 00:32:38 -0300
-Subject: [PATCH] ARM: sunxi: add PLL5 and PLL6 support
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This commit adds PLL5 and PLL6 nodes to the sun4i, sun5i and sun7i
-device trees.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
-Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun4i-a10.dtsi  | 19 +++++++++++++++++--
- arch/arm/boot/dts/sun5i-a10s.dtsi | 19 +++++++++++++++++--
- arch/arm/boot/dts/sun5i-a13.dtsi  | 19 +++++++++++++++++--
- arch/arm/boot/dts/sun7i-a20.dtsi  | 28 ++++++++++++++++------------
- 4 files changed, 67 insertions(+), 18 deletions(-)
-
---- a/arch/arm/boot/dts/sun4i-a10.dtsi
-+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
-@@ -73,6 +73,22 @@
-                       clocks = <&osc24M>;
-               };
- 
-+              pll5: pll5@01c20020 {
-+                      #clock-cells = <1>;
-+                      compatible = "allwinner,sun4i-pll5-clk";
-+                      reg = <0x01c20020 0x4>;
-+                      clocks = <&osc24M>;
-+                      clock-output-names = "pll5_ddr", "pll5_other";
-+              };
-+
-+              pll6: pll6@01c20028 {
-+                      #clock-cells = <1>;
-+                      compatible = "allwinner,sun4i-pll6-clk";
-+                      reg = <0x01c20028 0x4>;
-+                      clocks = <&osc24M>;
-+                      clock-output-names = "pll6_sata", "pll6_other", "pll6";
-+              };
-+
-               /* dummy is 200M */
-               cpu: cpu@01c20054 {
-                       #clock-cells = <0>;
-@@ -138,12 +154,11 @@
-                               "apb0_ir1", "apb0_keypad";
-               };
- 
--              /* dummy is pll62 */
-               apb1_mux: apb1_mux@01c20058 {
-                       #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-apb1-mux-clk";
-                       reg = <0x01c20058 0x4>;
--                      clocks = <&osc24M>, <&dummy>, <&osc32k>;
-+                      clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
-               };
- 
-               apb1: apb1@01c20058 {
---- a/arch/arm/boot/dts/sun5i-a10s.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
-@@ -70,6 +70,22 @@
-                       clocks = <&osc24M>;
-               };
- 
-+              pll5: pll5@01c20020 {
-+                      #clock-cells = <1>;
-+                      compatible = "allwinner,sun4i-pll5-clk";
-+                      reg = <0x01c20020 0x4>;
-+                      clocks = <&osc24M>;
-+                      clock-output-names = "pll5_ddr", "pll5_other";
-+              };
-+
-+              pll6: pll6@01c20028 {
-+                      #clock-cells = <1>;
-+                      compatible = "allwinner,sun4i-pll6-clk";
-+                      reg = <0x01c20028 0x4>;
-+                      clocks = <&osc24M>;
-+                      clock-output-names = "pll6_sata", "pll6_other", "pll6";
-+              };
-+
-               /* dummy is 200M */
-               cpu: cpu@01c20054 {
-                       #clock-cells = <0>;
-@@ -130,12 +146,11 @@
-                               "apb0_ir", "apb0_keypad";
-               };
- 
--              /* dummy is pll62 */
-               apb1_mux: apb1_mux@01c20058 {
-                       #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-apb1-mux-clk";
-                       reg = <0x01c20058 0x4>;
--                      clocks = <&osc24M>, <&dummy>, <&osc32k>;
-+                      clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
-               };
- 
-               apb1: apb1@01c20058 {
---- a/arch/arm/boot/dts/sun5i-a13.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
-@@ -74,6 +74,22 @@
-                       clocks = <&osc24M>;
-               };
- 
-+              pll5: pll5@01c20020 {
-+                      #clock-cells = <1>;
-+                      compatible = "allwinner,sun4i-pll5-clk";
-+                      reg = <0x01c20020 0x4>;
-+                      clocks = <&osc24M>;
-+                      clock-output-names = "pll5_ddr", "pll5_other";
-+              };
-+
-+              pll6: pll6@01c20028 {
-+                      #clock-cells = <1>;
-+                      compatible = "allwinner,sun4i-pll6-clk";
-+                      reg = <0x01c20028 0x4>;
-+                      clocks = <&osc24M>;
-+                      clock-output-names = "pll6_sata", "pll6_other", "pll6";
-+              };
-+
-               /* dummy is 200M */
-               cpu: cpu@01c20054 {
-                       #clock-cells = <0>;
-@@ -132,12 +148,11 @@
-                       clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
-               };
- 
--              /* dummy is pll6 */
-               apb1_mux: apb1_mux@01c20058 {
-                       #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-apb1-mux-clk";
-                       reg = <0x01c20058 0x4>;
--                      clocks = <&osc24M>, <&dummy>, <&osc32k>;
-+                      clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
-               };
- 
-               apb1: apb1@01c20058 {
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -69,23 +69,27 @@
-                       clocks = <&osc24M>;
-               };
- 
--              /*
--               * This is a dummy clock, to be used as placeholder on
--               * other mux clocks when a specific parent clock is not
--               * yet implemented. It should be dropped when the driver
--               * is complete.
--               */
--              pll6: pll6 {
--                      #clock-cells = <0>;
--                      compatible = "fixed-clock";
--                      clock-frequency = <0>;
-+              pll5: pll5@01c20020 {
-+                      #clock-cells = <1>;
-+                      compatible = "allwinner,sun4i-pll5-clk";
-+                      reg = <0x01c20020 0x4>;
-+                      clocks = <&osc24M>;
-+                      clock-output-names = "pll5_ddr", "pll5_other";
-+              };
-+
-+              pll6: pll6@01c20028 {
-+                      #clock-cells = <1>;
-+                      compatible = "allwinner,sun4i-pll6-clk";
-+                      reg = <0x01c20028 0x4>;
-+                      clocks = <&osc24M>;
-+                      clock-output-names = "pll6_sata", "pll6_other", "pll6";
-               };
- 
-               cpu: cpu@01c20054 {
-                       #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-cpu-clk";
-                       reg = <0x01c20054 0x4>;
--                      clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>;
-+                      clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
-               };
- 
-               axi: axi@01c20054 {
-@@ -144,7 +148,7 @@
-                       #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-apb1-mux-clk";
-                       reg = <0x01c20058 0x4>;
--                      clocks = <&osc24M>, <&pll6>, <&osc32k>;
-+                      clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
-               };
- 
-               apb1: apb1@01c20058 {