sunxi: 6.6: remove upstreamed patches

[openwrt/staging/blocktrron.git] / target / linux / sunxi / patches-6.6 / 002-v6.2-dt-bindings-phy-Add-special-clock-for-Allwinner-H616-PHY.patch

diff --git a/target/linux/sunxi/patches-6.6/002-v6.2-dt-bindings-phy-Add-special-clock-for-Allwinner-H616-PHY.patch b/target/linux/sunxi/patches-6.6/002-v6.2-dt-bindings-phy-Add-special-clock-for-Allwinner-H616-PHY.patch
deleted file mode 100644 (file)
index 5739172..0000000
--- a/target/linux/sunxi/patches-6.6/002-v6.2-dt-bindings-phy-Add-special-clock-for-Allwinner-H616-PHY.patch
+++ /dev/null
@@ -1,79 +0,0 @@
-From 6964affe65066651eca21e97247d3b7cac5153dc Mon Sep 17 00:00:00 2001
-From: Andre Przywara <andre.przywara@arm.com>
-Date: Mon, 31 Oct 2022 11:13:53 +0000
-Subject: [PATCH] dt-bindings: phy: Add special clock for Allwinner H616 PHY
-
-The USB PHY IP in the Allwinner H616 SoC requires a quirk that involves
-some resources from port 2's PHY and HCI IP. In particular the PMU clock
-for port 2 must be surely ungated before accessing the REG_HCI_PHY_CTL
-register of port 2. To allow each USB port to be controlled
-independently of port 2, we need a handle to that particular PMU clock
-in the *PHY* node, as the HCI and PHY part might be handled by separate
-drivers.
-
-Add that clock to the requirements of the H616 PHY binding, so that a
-PHY driver can apply the quirk in isolation, without requiring help from
-port 2's HCI driver.
-
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Reviewed-by: Rob Herring <robh@kernel.org>
-Link: https://lore.kernel.org/r/20221031111358.3387297-3-andre.przywara@arm.com
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
----
- .../phy/allwinner,sun8i-h3-usb-phy.yaml       | 26 +++++++++++++++++++
- 1 file changed, 26 insertions(+)
-
---- a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml
-+++ b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml
-@@ -36,18 +36,22 @@ properties:
-       - const: pmu3
- 
-   clocks:
-+    minItems: 4
-     items:
-       - description: USB OTG PHY bus clock
-       - description: USB Host 0 PHY bus clock
-       - description: USB Host 1 PHY bus clock
-       - description: USB Host 2 PHY bus clock
-+      - description: PMU clock for host port 2
- 
-   clock-names:
-+    minItems: 4
-     items:
-       - const: usb0_phy
-       - const: usb1_phy
-       - const: usb2_phy
-       - const: usb3_phy
-+      - const: pmu2_clk
- 
-   resets:
-     items:
-@@ -96,6 +100,28 @@ required:
-   - resets
-   - reset-names
- 
-+allOf:
-+  - if:
-+      properties:
-+        compatible:
-+          contains:
-+            enum:
-+              - allwinner,sun50i-h616-usb-phy
-+    then:
-+      properties:
-+        clocks:
-+          minItems: 5
-+
-+        clock-names:
-+          minItems: 5
-+    else:
-+      properties:
-+        clocks:
-+          maxItems: 4
-+
-+        clock-names:
-+          maxItems: 4
-+
- additionalProperties: false
- 
- examples: