X-Git-Url: http://git.openwrt.org/?a=blobdiff_plain;f=target%2Flinux%2Flantiq%2Ffiles-4.19%2Farch%2Fmips%2Fboot%2Fdts%2Flantiq%2Fvr9_arcadyan_vg3503j.dts;fp=target%2Flinux%2Flantiq%2Ffiles-4.19%2Farch%2Fmips%2Fboot%2Fdts%2Flantiq%2Fvr9_arcadyan_vg3503j.dts;h=e074147d66e7d243574b072bd3d20a40e1c9f706;hb=333b796c04d313cac56043b91461f083b71f8b45;hp=0000000000000000000000000000000000000000;hpb=154443754950578d6acfaf829f3c970b66e77cad;p=openwrt%2Fstaging%2Fmkresin.git

diff --git a/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vg3503j.dts b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vg3503j.dts
new file mode 100644
index 0000000000..e074147d66
--- /dev/null
+++ b/target/linux/lantiq/files-4.19/arch/mips/boot/dts/lantiq/vr9_arcadyan_vg3503j.dts
@@ -0,0 +1,144 @@
+/dts-v1/;
+
+#include "vr9.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/mips/lantiq_rcu_gphy.h>
+
+/ {
+	compatible = "arcadyan,vg3503j", "lantiq,xway", "lantiq,vr9";
+	model = "BT OpenReach VDSL Modem";
+
+	chosen {
+		bootargs = "console=ttyLTQ0,115200";
+	};
+
+	aliases {
+		led-boot = &power_green;
+		led-failsafe = &power_red;
+		led-running = &power_green;
+		led-upgrade = &power_green;
+
+		led-dsl = &dsl;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x2000000>;
+	};
+
+	keys {
+		compatible = "gpio-keys-polled";
+		poll-interval = <100>;
+		reset {
+			label = "reset";
+			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		power_red: power2 {
+			label = "vg3503j:red:power";
+			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
+		};
+		dsl: dsl {
+			label = "vg3503j:green:dsl";
+			gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
+		};
+		power_green: power {
+			label = "vg3503j:green:power";
+			gpios = <&gpio 28 GPIO_ACTIVE_LOW>;
+			default-state = "keep";
+		};
+	};
+};
+
+&eth0 {
+	pinctrl-0 = <&mdio_pins>,
+		    <&gphy0_led0_pins>, <&gphy0_led1_pins>, <&gphy0_led2_pins>,
+		    <&gphy1_led0_pins>, <&gphy1_led1_pins>, <&gphy1_led2_pins>;
+
+	interface@0 {
+		compatible = "lantiq,xrx200-pdi";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0>;
+
+		lantiq,switch;
+		ethernet@2 {
+			compatible = "lantiq,xrx200-pdi-port";
+			reg = <2>;
+			phy-mode = "mii";
+			phy-handle = <&phy11>;
+		};
+		ethernet@4 {
+			compatible = "lantiq,xrx200-pdi-port";
+			reg = <4>;
+			phy-mode = "mii";
+			phy-handle = <&phy13>;
+		};
+	};
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "lantiq,xrx200-mdio";
+
+		phy11: ethernet-phy@11 {
+			reg = <0x11>;
+			compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
+			lantiq,led1h = <0x70>;
+			lantiq,led1l = <0x00>;
+			lantiq,led2h = <0x00>;
+			lantiq,led2l = <0x03>;
+		};
+		phy13: ethernet-phy@13 {
+			reg = <0x13>;
+			compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
+			lantiq,led1h = <0x70>;
+			lantiq,led1l = <0x00>;
+			lantiq,led2h = <0x00>;
+			lantiq,led2l = <0x03>;
+		};
+	};
+};
+
+&gphy0 {
+	lantiq,gphy-mode = <GPHY_MODE_GE>;
+};
+
+&gphy1 {
+	lantiq,gphy-mode = <GPHY_MODE_GE>;
+};
+
+&localbus {
+	flash@0 {
+		compatible = "lantiq,nor";
+		bank-width = <2>;
+		reg = <0 0x0 0x2000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "uboot";
+				reg = <0x00000 0x20000>;
+			};
+
+			partition@20000 {
+				label = "firmware";
+				reg = <0x20000 0x7d0000>;
+			};
+
+			partition@7f0000 {
+				label = "uboot-env";
+				reg = <0x7f0000 0x10000>;
+			};
+		};
+	};
+};