X-Git-Url: http://git.openwrt.org/?a=blobdiff_plain;f=target%2Flinux%2Framips%2Fdts%2Fmt7621.dtsi;h=3e86a7894abc610e510dc2a9dd3059b95a95e772;hb=a3764ee29dd09394fa750c78160e300d86532561;hp=09124072bd7e6e9e3c23095ba7744558587f0b71;hpb=ac11f36b337da29f422d16776cf36c98013dcc77;p=openwrt%2Fstaging%2Fmkresin.git

diff --git a/target/linux/ramips/dts/mt7621.dtsi b/target/linux/ramips/dts/mt7621.dtsi
index 09124072bd..3e86a7894a 100644
--- a/target/linux/ramips/dts/mt7621.dtsi
+++ b/target/linux/ramips/dts/mt7621.dtsi
@@ -41,12 +41,14 @@
 		bootargs = "console=ttyS0,57600";
 	};
 
+#ifdef DTS_LEGACY
 	pll: pll {
 		compatible = "mediatek,mt7621-pll", "syscon";
 
 		#clock-cells = <1>;
 		clock-output-names = "cpu", "bus";
 	};
+#endif
 
 	sysclock: sysclock {
 		#clock-cells = <0>;
@@ -65,7 +67,16 @@
 		#size-cells = <1>;
 
 		sysc: syscon@0 {
+#ifdef DTS_LEGACY
 			compatible = "mtk,mt7621-sysc", "syscon";
+#else
+			compatible = "mediatek,mt7621-sysc", "syscon";
+			#clock-cells = <1>;
+			ralink,memctl = <&memc>;
+			clock-output-names = "xtal", "cpu", "bus",
+					     "50m", "125m", "150m",
+					     "250m", "270m";
+#endif
 			reg = <0x0 0x100>;
 		};
 
@@ -79,6 +90,7 @@
 			#interrupt-cells = <2>;
 			compatible = "mediatek,mt7621-gpio";
 			gpio-controller;
+			gpio-ranges = <&pinctrl 0 0 95>;
 			interrupt-controller;
 			reg = <0x600 0x100>;
 			interrupt-parent = <&gic>;
@@ -137,7 +149,11 @@
 		};
 
 		memc: syscon@5000 {
+#ifdef DTS_LEGACY
 			compatible = "mtk,mt7621-memc", "syscon";
+#else
+			compatible = "mediatek,mt7621-memc", "syscon";
+#endif
 			reg = <0x5000 0x1000>;
 		};
 
@@ -197,7 +213,11 @@
 			compatible = "ralink,mt7621-spi";
 			reg = <0xb00 0x100>;
 
+#ifdef DTS_LEGACY
 			clocks = <&pll MT7621_CLK_BUS>;
+#else
+			clocks = <&sysc MT7621_CLK_BUS>;
+#endif
 
 			resets = <&rstctrl 18>;
 			reset-names = "spi";
@@ -405,7 +425,11 @@
 		timer {
 			compatible = "mti,gic-timer";
 			interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
+#ifdef DTS_LEGACY
 			clocks = <&pll MT7621_CLK_CPU>;
+#else
+			clocks = <&sysc MT7621_CLK_CPU>;
+#endif
 		};
 	};
 
@@ -442,13 +466,19 @@
 		compatible = "mediatek,mt7621-eth";
 		reg = <0x1e100000 0x10000>;
 
+#ifdef DTS_LEGACY
 		clocks = <&sysclock>;
 		clock-names = "ethif";
+#else
+		clocks = <&sysc MT7621_CLK_FE>,
+			 <&sysc MT7621_CLK_ETH>;
+		clock-names = "fe", "ethif";
+#endif
 
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		resets = <&rstctrl 6 &rstctrl 23>;
+		resets = <&rstctrl 6>, <&rstctrl 23>;
 		reset-names = "fe", "eth";
 
 		interrupt-parent = <&gic>;
@@ -456,8 +486,10 @@
 
 		mediatek,ethsys = <&sysc>;
 
+#ifdef DTS_LEGACY
 		pinctrl-names = "default";
 		pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>;
+#endif
 
 		gmac0: mac@0 {
 			compatible = "mediatek,eth-mac";
@@ -557,15 +589,22 @@
 
 		device_type = "pci";
 
+#ifdef DTS_LEGACY
 		ranges = <0x02000000 0 0x00000000 0x60000000 0 0x10000000>, /* pci memory */
 			 <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */
+#else
+		ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
+			 <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */
+#endif
+
+		status = "disabled";
 
+#ifdef DTS_LEGACY
 		interrupt-parent = <&gic>;
 		interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
 				GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
 				GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 
-		status = "disabled";
 
 		resets = <&rstctrl 24>, <&rstctrl 25>, <&rstctrl 26>;
 		reset-names = "pcie0", "pcie1", "pcie2";
@@ -573,6 +612,13 @@
 		clock-names = "pcie0", "pcie1", "pcie2";
 		phys = <&pcie0_phy 1>, <&pcie2_phy 0>;
 		phy-names = "pcie-phy0", "pcie-phy2";
+#else
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0xF800 0 0 0>;
+		interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
+				<0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
+				<0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
+#endif
 
 		reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 
@@ -582,6 +628,15 @@
 			#size-cells = <2>;
 			device_type = "pci";
 			ranges;
+#ifndef DTS_LEGACY
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0>;
+			interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
+			resets = <&rstctrl 24>;
+			clocks = <&sysc MT7621_CLK_PCIE0>;
+			phys = <&pcie0_phy 1>;
+			phy-names = "pcie-phy0";
+#endif
 		};
 
 		pcie1: pcie@1,0 {
@@ -590,6 +645,15 @@
 			#size-cells = <2>;
 			device_type = "pci";
 			ranges;
+#ifndef DTS_LEGACY
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0>;
+			interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
+			resets = <&rstctrl 25>;
+			clocks = <&sysc MT7621_CLK_PCIE1>;
+			phys = <&pcie0_phy 1>;
+			phy-names = "pcie-phy1";
+#endif
 		};
 
 		pcie2: pcie@2,0 {
@@ -598,18 +662,33 @@
 			#size-cells = <2>;
 			device_type = "pci";
 			ranges;
+#ifndef DTS_LEGACY
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0>;
+			interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
+			resets = <&rstctrl 26>;
+			clocks = <&sysc MT7621_CLK_PCIE2>;
+			phys = <&pcie2_phy 0>;
+			phy-names = "pcie-phy2";
+#endif
 		};
 	};
 
 	pcie0_phy: pcie-phy@1e149000 {
 		compatible = "mediatek,mt7621-pci-phy";
 		reg = <0x1e149000 0x0700>;
+#ifndef DTS_LEGACY
+		clocks = <&sysc MT7621_CLK_XTAL>;
+#endif
 		#phy-cells = <1>;
 	};
 
 	pcie2_phy: pcie-phy@1e14a000 {
 		compatible = "mediatek,mt7621-pci-phy";
 		reg = <0x1e14a000 0x0700>;
+#ifndef DTS_LEGACY
+		clocks = <&sysc MT7621_CLK_XTAL>;
+#endif
 		#phy-cells = <1>;
 	};
 };