X-Git-Url: http://git.openwrt.org/?a=blobdiff_plain;f=target%2Flinux%2Framips%2Fdts%2Frt3050.dtsi;h=30a3f898cd064dfc0c029cc66b8d1f1e1b879417;hb=HEAD;hp=bd51838bacdbb93457531e089e70bff2388ac310;hpb=eda27d755729b65e3620e60dc0340a39b0d9e0f1;p=openwrt%2Fstaging%2Fwigyori.git diff --git a/target/linux/ramips/dts/rt3050.dtsi b/target/linux/ramips/dts/rt3050.dtsi index bd51838bac..30a3f898cd 100644 --- a/target/linux/ramips/dts/rt3050.dtsi +++ b/target/linux/ramips/dts/rt3050.dtsi @@ -1,11 +1,22 @@ +/dts-v1/; + / { #address-cells = <1>; #size-cells = <1>; compatible = "ralink,rt3050-soc", "ralink,rt3052-soc", "ralink,rt3350-soc"; + aliases { + spi0 = &spi0; + serial0 = &uartlite; + }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { compatible = "mips,mips24KEc"; + reg = <0>; }; }; @@ -13,12 +24,7 @@ bootargs = "console=ttyS0,57600"; }; - aliases { - spi0 = &spi0; - serial0 = &uartlite; - }; - - cpuintc: cpuintc@0 { + cpuintc: cpuintc { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller; @@ -33,15 +39,19 @@ #address-cells = <1>; #size-cells = <1>; - sysc: sysc@0 { - compatible = "ralink,rt3050-sysc", "syscon"; + sysc: syscon@0 { + compatible = "ralink,rt3050-sysc", "ralink,rt3052-sysc", "syscon"; reg = <0x0 0x100>; + #clock-cells = <1>; + #reset-cells = <1>; }; timer: timer@100 { compatible = "ralink,rt3050-timer", "ralink,rt2880-timer"; reg = <0x100 0x20>; + clocks = <&sysc 3>; + interrupt-parent = <&intc>; interrupts = <1>; }; @@ -50,7 +60,9 @@ compatible = "ralink,rt3050-wdt", "ralink,rt2880-wdt"; reg = <0x120 0x10>; - resets = <&rstctrl 8>; + clocks = <&sysc 4>; + + resets = <&sysc 8>; reset-names = "wdt"; interrupt-parent = <&intc>; @@ -61,9 +73,6 @@ compatible = "ralink,rt3050-intc", "ralink,rt2880-intc"; reg = <0x200 0x100>; - resets = <&rstctrl 19>; - reset-names = "intc"; - interrupt-controller; #interrupt-cells = <1>; @@ -75,9 +84,6 @@ compatible = "ralink,rt3050-memc"; reg = <0x300 0x100>; - resets = <&rstctrl 20>; - reset-names = "mc"; - interrupt-parent = <&intc>; interrupts = <3>; }; @@ -86,8 +92,9 @@ compatible = "ralink,rt3050-uart", "ralink,rt2880-uart", "ns16550a"; reg = <0x500 0x100>; - resets = <&rstctrl 12>; - reset-names = "uart"; + clocks = <&sysc 5>; + + resets = <&sysc 12>; interrupt-parent = <&intc>; interrupts = <5>; @@ -104,15 +111,12 @@ gpio-controller; #gpio-cells = <2>; + ngpios = <24>; ralink,gpio-base = <0>; - ralink,num-gpios = <24>; ralink,register-map = [ 00 04 08 0c 20 24 28 2c 30 34 ]; - resets = <&rstctrl 13>; - reset-names = "pio"; - interrupt-parent = <&intc>; interrupts = <6>; }; @@ -124,8 +128,8 @@ gpio-controller; #gpio-cells = <2>; + ngpios = <16>; ralink,gpio-base = <24>; - ralink,num-gpios = <16>; ralink,register-map = [ 00 04 08 0c 10 14 18 1c 20 24 ]; @@ -140,8 +144,8 @@ gpio-controller; #gpio-cells = <2>; + ngpios = <12>; ralink,gpio-base = <40>; - ralink,num-gpios = <12>; ralink,register-map = [ 00 04 08 0c 10 14 18 1c 20 24 ]; @@ -153,7 +157,7 @@ compatible = "ralink,rt305x-gdma"; reg = <0x700 0x100>; - resets = <&rstctrl 14>; + resets = <&sysc 14>; reset-names = "dma"; interrupt-parent = <&intc>; @@ -170,7 +174,9 @@ compatible = "ralink,rt2880-i2c"; reg = <0x900 0x100>; - resets = <&rstctrl 16>; + clocks = <&sysc 6>; + + resets = <&sysc 16>; reset-names = "i2c"; #address-cells = <1>; @@ -186,7 +192,9 @@ compatible = "ralink,rt3050-i2s"; reg = <0xa00 0x100>; - resets = <&rstctrl 17>; + clocks = <&sysc 7>; + + resets = <&sysc 17>; reset-names = "i2s"; interrupt-parent = <&intc>; @@ -204,9 +212,11 @@ compatible = "ralink,rt3050-spi", "ralink,rt2880-spi"; reg = <0xb00 0x100>; - resets = <&rstctrl 18>; + resets = <&sysc 18>; reset-names = "spi"; + clocks = <&sysc 8>; + #address-cells = <1>; #size-cells = <0>; @@ -220,8 +230,9 @@ compatible = "ralink,rt3050-uart", "ralink,rt2880-uart", "ns16550a"; reg = <0xc00 0x100>; - resets = <&rstctrl 19>; - reset-names = "uartl"; + clocks = <&sysc 10>; + + resets = <&sysc 19>; interrupt-parent = <&intc>; interrupts = <12>; @@ -241,67 +252,57 @@ state_default: pinctrl0 { sdram { - ralink,group = "sdram"; - ralink,function = "sdram"; + groups = "sdram"; + function = "sdram"; }; }; - i2c_pins: i2c { - i2c { - ralink,group = "i2c"; - ralink,function = "i2c"; + i2c_pins: i2c_pins { + i2c_pins { + groups = "i2c"; + function = "i2c"; }; }; - spi_pins: spi { - spi { - ralink,group = "spi"; - ralink,function = "spi"; + spi_pins: spi_pins { + spi_pins { + groups = "spi"; + function = "spi"; }; }; rgmii_pins: rgmii { rgmii { - ralink,group = "rgmii"; - ralink,function = "rgmii"; + groups = "rgmii"; + function = "rgmii"; }; }; uartlite_pins: uartlite { uart { - ralink,group = "uartlite"; - ralink,function = "uartlite"; + groups = "uartlite"; + function = "uartlite"; }; }; }; - rstctrl: rstctrl { - compatible = "ralink,rt3050-reset", "ralink,rt2880-reset"; - #reset-cells = <1>; - }; - - clkctrl: clkctrl { - compatible = "ralink,rt2880-clock"; - #clock-cells = <1>; - }; - usbphy: usbphy { compatible = "ralink,rt3050-usbphy"; #phy-cells = <0>; ralink,sysctl = <&sysc>; - resets = <&rstctrl 22>; + resets = <&sysc 22>; reset-names = "host"; - clocks = <&clkctrl 18>; - clock-names = "host"; }; ethernet: ethernet@10100000 { compatible = "ralink,rt3050-eth"; reg = <0x10100000 0x10000>; - resets = <&rstctrl 21>; - reset-names = "fe"; + clocks = <&sysc 11>; + + resets = <&sysc 21>, <&sysc 23>; + reset-names = "fe", "esw"; interrupt-parent = <&cpuintc>; interrupts = <5>; @@ -313,8 +314,8 @@ compatible = "ralink,rt3050-esw"; reg = <0x10110000 0x8000>; - resets = <&rstctrl 23>; - reset-names = "esw"; + resets = <&sysc 24>; + reset-names = "ephy"; interrupt-parent = <&intc>; interrupts = <17>; @@ -324,6 +325,8 @@ compatible = "ralink,rt3050-wmac", "ralink,rt2880-wmac"; reg = <0x10180000 0x40000>; + clocks = <&sysc 12>; + interrupt-parent = <&cpuintc>; interrupts = <6>; @@ -331,15 +334,22 @@ }; otg: otg@101c0000 { + #address-cells = <1>; + #size-cells = <0>; compatible = "ralink,rt3050-otg", "snps,dwc2"; reg = <0x101c0000 0x40000>; interrupt-parent = <&intc>; interrupts = <18>; - resets = <&rstctrl 22>; + resets = <&sysc 22>; reset-names = "otg"; status = "disabled"; + + otg_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; }; };